MC10E154FNG ON Semiconductor

MC10E154, MC100E154 5V ECL 5-Bit 2:1 Mux-Latch Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is MC10E154, MC100E154 D D D D V Q Q 4b 4a 3b 3a CCO 4 4 25 24 23 22 21 20 19 SEL Q 26 18 3 LEN1 Q 17 27 3 LEN2 28 16 V CC V 1 15 Q EE 2 28-Lead PLCC (Top View) MR 2 14 Q 2 D 3 13 Q 0a 1 D 0b 4 Q 12 1 56 7 8 9 10 11 D D D D V Q Q 1a 1b 2a 2b CCO 0 0 * All V and V pins are tied together on the die. CC CCO Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. Figure 1. 28Lead Pinout Q D Q Table 1. PIN DESCRIPTION 0a 0 D MUX EN Q PIN FUNCTION Q D R 0 SEL 0b D D ECL Input Data a 0a 4a Q D Q 1a 1 D D ECL Input Data b D 0b 4b MUX EN Q Q SEL ECL Data Select Input D SEL R 1 1b LEN1, LEN2 ECL Latch Enables Q Q D 2 2a D MUX MR ECL Master Reset EN Q Q D SEL R 2 Q Q , Q Q ECL Differential Outputs 2b 0 4 0 4 V , V Positive Supply CC CCO Q D 3a Q 3 MUX D V Negative Supply EE EN Q Q D SEL R 3 3b Table 2. TRUTH TABLE D Q 4a Q 4 MUX D SEL DATA EN Q Q SEL D R 4 4b H a L b SEL LEN1 LEN2 MR Figure 2. Logic Diagram