MC10E195FNR2G ON Semiconductor

MC10E195, MC100E195 5V ECL Programmable Delay Chip The MC10E/100E195 is a programmable delay chip (PDC) designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. MC10E195, MC100E195 LOGIC DIAGRAM AND PINOUT ASSIGNMENT PIN DESCRIPTION D2 D3 D4 D5 D6 D7 NC PIN FUNCTION 25 24 23 22 21 20 19 IN/IN ECL Signal Input D1 18 NC 26 EN ECL Input Enable 17 NC D0 27 D 0:7 ECL MUX Select Inputs LEN 28 16 V Q/Q ECL Signal Output CC LEN ECL Latch Enable V 15 V EE 1 CCO MC10E195 SET MIN ECL Min Delay Set MC100E195 IN 14 Q 2 SET MAX ECL Max Delay Set IN 13 Q 3 CASCADE, CASCADE ECL Cascade Signal V Reference Voltage Output V 12 V 4 BB BB CCO V , V Positive Supply CC CCO 56 7 8 9 10 11 V Negative Supply EE NC NC EN NC No Connect Figure 1. Pinout:28-Lead PLCC (Top View) * All V and V pins are tied together on the die. CC CCO Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. TRUTH TABLE EN L Q = IN EN H Q Logic Low LEN L Pass Through D 0:10 LEN H Latch D 0:10 SETMIN L Normal Mode SETMIN H Min Delay Path SETMAX L Normal Mode SETMAX H Max Delay Path V BB 1 1 0 0 0 0 0 0 0 IN 4 GATES 8 GATES 16 GATES IN 1 1 111 1 1 1 1 1 0 Q EN * 1.25 * 1.5 Q 1 1 V EE CASCADE LEN Q LEN 7 BIT LATCH SET MIN LATCH SET MAX D CASCADE CASCADE D0 D1 D2 D3 D4 D5 D6 D7 * DELAYS ARE 25% OR 50% LONGER THAN * STANDARD (STANDARD 80 PS) Figure 2. LOGIC DIAGRAM SIMPLIFIED