MC10E211, MC100E211 5 VECL 1:6 Differential Clock Distribution Chip Description The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. www.onsemi.com The E211 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open in which case it will be pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. Both a common enable and individual output enables are provided. PLCC28 When asserted the positive output will go LOW on the next negative FN SUFFIX transition of the CLK (or SCLK) input. The enabling function is CASE 77602 synchronous so that the outputs will only be enabled/disabled when the outputs are already in the LOW state. In this way the problem of MARKING DIAGRAM* runt pulse generation during the disable operation is avoided. Note that 1 the internal flip flop is clocked on the falling edge of the input clock edge, therefore all associated specifications are referenced to the negative edge of the CLK input. The output transitions of the E211 are faster than the standard MCxxxE211FNG ECLinPS edge rates. This feature provides a means of distributing AWLYYWW higher frequency signals than capable with the E111 device. Because of these edge rates and the tight skew limits guaranteed in the specification, there are certain termination guidelines which must be xxx = 10 or 100 followed. For more details on the recommended termination schemes A = Assembly Location please refer to the applications information section of this data sheet. WL = Wafer Lot The V pin, an internally generated voltage supply, is available to BB YY = Year WW = Work Week this device only. For single-ended input conditions, the unused G = Pb-Free Package differential input is connected to V as a switching reference voltage. BB *For additional marking information, refer to V may also rebias AC coupled inputs. When used, decouple V BB BB Application Note AND8002/D. and V via a 0.01 F capacitor and limit current sourcing or sinking CC to 0.5 mA. When not used, V should be left open. BB ORDERING INFORMATION The 100 Series contains temperature compensation. Device Package Shipping Features Guaranteed Low Skew Specification MC10E211FNG PLCC28 37 Units/Tube (Pb-Free) Synchronous Enabling/Disabling MC100E211FNG PLCC28 37 Units/Tube Multiplexed Clock Inputs (Pb-Free) V Output for Single-Ended Use BB Common and Individual Enable/Disable Control Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test High Bandwidth Output Transistors Moisture Sensitivity Level: 3 (Pb-Free) PECL Mode Operating Range: For Additional Information, see Application Note V = 4.2 V to 5.7 V with V = 0 V CC EE AND8003/D NECL Mode Operating Range: Flammability Rating: V = 0 V with V = 4.2 V to 5.7 V CC EE UL 94 V0 0.125 in, Oxygen Index: 28 to 34 Internal Input 75 k Pulldown Resistors Transistor Count = 457 devices ESD Protection: These Devices are Pb-Free, Halogen Free and are Human Body Model > 2 kV RoHS Compliant Machine Model > 100 V Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 13 MC10E211/DMC10E211, MC100E211 EN4 EN5 V Q5 Q5 Q4 Q4 CC0 Table 1. PIN DESCRIPTION 25 24 23 22 21 20 19 PIN FUNCTION 18 EN3 26 Q3 EN0EN5 ECL Enable SEL ECL Select (Clock) SEL 27 17 Q3 SCLK ECL Single Clock CLK, CLK ECL Differential Clock SCLK 16 V CEN ECL Common Enable 28 CC Q0Q5, Q0Q5 ECL Differential Outputs V Reference Voltage Output BB V 1 15 Q2 EE V , V Positive Supply CC CCO V Negative Supply EE CLK 2 14 Q2 NC No Connect CLK 3 13 Q1 V 4 12 Q1 BB 5 6 7 8 9 10 11 CEN EN2 EN1 EN0 V Q0 Q0 CC0 *All V and V pins are tied together on the die. CC CCO Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. Figure 1. Pinout: PLCC-28 (Top View) Q0 Table 2. FUNCTION TABLE Q0 CLK SCLK SEL ENx Q EN0 H/L X L L CLK D Q X H/L H L SCLK Z* Z* X H L *Z = Negative transition of CLK or SCLK BITS 14 CLK 0 CLK Q14 1 SCLK Q14 SEL DQ EN14 CEN Q5 Q5 EN5 D Q V BB Figure 2. Logic Diagram www.onsemi.com 2