MC10E452, MC100E452 5 VECL 5Bit Differential Register Description The MC10E/100E452 is a 5-bit differential register with differential data (inputs and outputs) and clock. The registers are triggered by a www.onsemi.com positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of PLCC28 the inputs. Because of the edge triggered flip-flop nature of the device FN SUFFIX simultaneously opening both the clock and data inputs will result in an CASE 77602 output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below V . CC The fully differential design of the device makes it ideal for very MARKING DIAGRAM* high frequency applications where a registered data path is necessary. The V pin, an internally generated voltage supply, is available to 128 BB this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB MCxxxE452FNG and V via a 0.01 F capacitor and limit current sourcing or sinking CC AWLYYWW to 0.5 mA. When not used, V should be left open. BB The 100 Series contains temperature compensation. Features xxx = 10 or 100 Differential D, CLK and Q V Reference Available BB A = Assembly Location WL = Wafer Lot 1100 MHz Min. Toggle Frequency YY = Year Asynchronous Master Reset WW = Work Week PECL Mode Operating Range: G = Pb-Free Package V = 4.2 V to 5.7 V with V = 0 V CC EE *For additional marking information, refer to NECL Mode Operating Range: Application Note AND8002/D. V = 0 V with V = 4.2 V to 5.7 V CC EE Internal Input 50 k Pulldown Resistors, Output Q will Default to 3 Low State When Inputs Are Left Open ORDERING INFORMATION ESD Protection: Human Body Model > 2 kV Device Package Shipping Machine Model > 200 V MC10E452FNR2G PLCC28 500/Tape & Reel Charged Device Model > 2 kV (Pb-Free) Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test MC100E452FNG PLCC28 37 Units/Tube (Pb-Free) Moisture Sensitivity Level: 3 (Pb-Free) For Additional Information, see Application Note AND8003/D For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer Flammability Rating: to our Tape and Reel Packaging Specifications UL 94 V0 0.125 in,Oxygen Index: 28 to 34 Brochure, BRD8011/D. Transistor Count = 315 devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 12 MC10E452/DMC10E452, MC100E452 D D D D V Q Q 3 3 4 4 CCO 4 4 Table 1. PIN DESCRIPTION 25 24 23 22 21 20 19 PIN FUNCTION 18 Q MR 26 3 D 0:4 , D 0:4 ECL Differential Data Inputs 17 Q CLK 27 3 MR ECL Master Reset Input 28 V CLK, CLK ECL Differential Clock Input CLK 16 CC 1 Q 0:4 , Q 0:4 ECL Differential Data Outputs V 15 Q EE 2 V Reference Voltage Output BB V 2 14 Q BB 2 V , V Positive Supply CC CCO D 3 13 2 Q 1 V Negative Supply EE D Q 4 12 2 1 567 89 10 11 D D D D V Q Q 1 1 0 0 CCO 0 0 * All V and V pins are tied together on the die. CC CCO Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. Figure 1. Pinout: PLCC28 (Top View) D 0 DQ Q 0 D 0 Q 0 R D 1 DQ Q 1 D 1 Q 1 R D 2 Q D Q 2 D 2 Q 2 R D 3 Q Q D 3 D 3 Q 3 R D 4 Q DQ 4 D 4 Q 4 CLK R CLK MR V BB Figure 2. Logic Diagram www.onsemi.com 2