3.3 VECL Triple D FlipFlop with Set and Reset MC100LVEL30 Description The MC100LVEL30 is a triple master-slave D flip-flop with www.onsemi.com differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided for each flip-flop. Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs. Features SOIC20 WB DW SUFFIX 1200 MHz Minimum Toggle Frequency CASE 751D05 450 ps Typical Propagation Delays ESD Protection: > 2 kV Human Body Model MARKING DIAGRAM* The 100 Series Contains Temperature Compensation. PECL Mode Operating Range: 20 V = 3.0 V to 3.8 V with V = 0 V CC EE NECL Mode Operating Range: 100LVEL30 V = 0 V with V = 3.0 V to 3.8 V AWLYYWWG CC EE Internal Input 75 k Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1 Moisture Sensitivity: Level 3 (Pb-Free) A = Assembly Location (For Additional Information, see Application Note AND8003/D) WL = Wafer Lot Flammability Rating: UL 94 V0 0.125 in, YY = Year WW = Work Week Oxygen Index: 28 to 34 G = Pb-Free Package Transistor Count = 347 Devices *For additional marking information, refer to These Devices are Pb-Free, Halogen Free and are RoHS Compliant Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100LVEL30DWR2G 1000 / SOIC20 WB (Pb-Free) Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2021 Rev. 9 MC100LVEL30/DMC100LVEL30 V Q0 Q0 V Q1 Q1 V Q2 Q2 V CC CC CC EE 20 19 18 17 16 15 14 13 12 11 Q Q Q Q Q Q S R S R S R D D D 1 2 3 4 5678 9 10 S012 D0 CLK0 R0 D1 CLK1 R1 D2 CLK2 R2 Warning: All V and V pins must be externally connected to CC EE Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View) Table 2. PIN DESCRIPTION Table 1. TRUTH TABLE PIN FUNCTION R S D CLK Q Q D0D2 ECL Data Inputs R0R2 ECL Reset Inputs L H L L L Z H L L L H Z CLK0CLK2 ECL Clock Inputs L H H L X X S012 ECL Common Set Input H L L H X X Q0Q2 Q0Q2 ECL Differential Data Outputs Undef Undef H H X X V Positive Supply CC Z = LOW to HIGH Transition V Negative Supply EE X = Dont Care Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 to 0 V CC EE V NECL Mode Power Supply V = 0 V 8 to 0 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 to 0 CC I EE I Output Current Continuous 50 mA out Surge 100 T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC20 WB 90 C/W JA 500 lfpm SOIC20 WB 60 Thermal Resistance (Junction-to-Case) Standard Board SOIC20 WB 30 to 35 C/W JC T Wave Solder < 2 to 3 sec 248C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2