MC100LVEL33 3.3 V ECL 4 Divider Description The MC100LVEL33 is an integrated 4 divider. The LVEL is functionally equivalent to the EL33 and works from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. www.onsemi.com Upon power-up, the internal flip-flops will attain a random state the reset allows for the synchronization of multiple LVEL33s in a system. The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused 8 8 differential input is connected to V as a switching reference voltage. BB 1 1 V may also rebias AC coupled inputs. When used, decouple V BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC SOIC8 NB TSSOP8 to 0.5 mA. When not used, V should be left open. BB D SUFFIX DT SUFFIX CASE 75107 CASE 948R02 Features 630 ps Typical Propagation Delay MARKING DIAGRAMS* 4.0 GHz Typical Maximum Frequency ESD Protection: 8 8 > 4 KV Human Body Model KVL33 KV33 > 200 V Machine Model ALYW ALYW The 100 Series Contains Temperature Compensation 1 1 PECL Mode Operating Range: V = 3.0 V to 3.8 V CC with V = 0 V EE SOIC8 TSSOP8 NECL Mode Operating Range: V = 0 V CC A = Assembly Location with V = 3.0 V to 3.8 V EE L = Wafer Lot Internal Input Pulldown Resistors Y = Year W = Work Week Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test M = Date Code Moisture Sensitivity: = Pb-Free Package Level 1 for SOIC8 (Note: Microdot may be in either location) Level 3 for TSSOP8 *For additional marking information, refer to Application Note AND8002/D. For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V0 0.125 in, Oxygen Index: 28 to 34 ORDERING INFORMATION Transistor Count = 130 Devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant Device Package Shipping MC100LVEL33DG SOIC8 NB 98 Units / Tube (Pb-Free) MC100LVEL33DR2G 2500Tape & Reel SOIC8 NB (Pb-Free) MC100LVEL33DTG TSSOP8 100 Units / Tube (Pb-Free) MC100LVEL33DTR2G TSSOP8 2500 Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 6 MC100LVEL33/DMC100LVEL33 Table 1. PIN DESCRIPTION Reset 1 8 V CC PIN FUNCTION R CLK*, CLK** ECL Differential Clock Inputs CLK 2 7 Q Q, Q ECL Differential Data 4 Outputs Reset* ECL Asynch Reset 4 V Reference Voltage Output BB V Positive Supply CLK 3 6 Q CC V Negative Supply EE * Pins will default LOW when open due to internal 75 k V 4 5 V resistor to V BB EE EE ** Pins will default to 1/2 V when open due to internal CC resistors: 75 k to V and 75 k to V EE CC Figure 1. Logic Diagram and Pinout Assignment Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 to 0 V CC EE V NECL Mode Power Supply V = 0 V 8 to 0 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 to 0 CC I EE I Output Current Continuous 50 mA out Surge 100 I V Sink/Source 0.5 mA BB BB T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8 NB 190 C/W JA 500 lfpm SOIC8 NB 130 Thermal Resistance (Junction-to-Case) Standard Board SOIC8 NB 41 to 44 5% C/W JC Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP8 185 C/W JA 500 lfpm TSSOP8 140 Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 5% C/W JC T Wave Solder (Pb-Free) < 2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2