3.3 V ECL D FlipFlop with Set and Reset MC100LVEL31 Description The MC100LVEL31 is a D flip-flop with set and reset. The device is www.onsemi.com functionally equivalent to the EL31 device but operates from a 3.3 V supply. With propagation delays and output transition times essentially equivalent to the EL31, the LVEL31 is ideally suited for those applications which require the ultimate in AC performance at low power 8 supply voltages. 8 1 1 Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when clock is LOW and is SOIC8 NB TSSOP8 transferred to the slave, and thus the outputs, upon a positive transition of D SUFFIX DT SUFFIX the clock. CASE 75107 CASE 948R02 Features 475 ps Typical Propagation Delay MARKING DIAGRAMS* 2.9 GHz Toggle Frequency ESD Protection: 8 8 > 4 kV Human Body Model KVL31 KV31 > 200 V Machine Model ALYW ALYW The 100 Series Contains Temperature Compensation 1 1 PECL Mode Operating Range: V = 3.0 V to 3.8 V CC with V = 0 V EE SOIC8 NB TSSOP8 NECL Mode Operating Range: V = 0 V CC A = Assembly Location with V = 3.0 V to 3.8 V EE L = Wafer Lot Internal Input Pulldown Resistors Y = Year Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test W = Work Week M = Date Code Moisture Sensitivity: = Pb-Free Package Level 1 for SOIC8 (Note: Microdot may be in either location) Level 3 for TSSOP8 *For additional marking information, refer to For Additional Information, see Application Note AND8003/D Application Note AND8002/D. Flammability Rating: UL 94 V0 0.125 in, Oxygen Index: 28 to 34 ORDERING INFORMATION Transistor Count = 121 Devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant Device Package Shipping MC100LVEL31DG SOIC8 NB 98 Units / Tube (Pb-Free) MC100LVEL31DTG TSSOP8 100 Units / Tube (Pb-Free) MC100LVEL31DTR2G TSSOP8 2500 / (Pb-Free) Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2021 Rev. 6 MC100LVEL31/DMC100LVEL31 S 1 8 V CC S D 2 7 Q D Flip Flop CLK 3 6 Q R R45 V EE Figure 1. Logic Diagram and Pinout Assignment Table 1. PIN DESCRIPTION Table 2. TRUTH TABLE PIN FUNCTION D S R CLK Q Q CLK ECL Clock Input L L L Z L H Q, Q ECL Differential Data Outputs H L L Z H L D ECL Data Input X H L X H L X L H X L H R ECL Reset Input X H H X Undef Undef S ECL Set Input V Positive Supply CC Z = LOW to HIGH Transition X = Dont Care V Negative Supply EE Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 to 0 V CC EE V NECL Mode Power Supply V = 0 V 8 to 0 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 to 0 CC I EE I Output Current Continuous 50 mA out Surge 100 T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8 NB 190 C/W JA 500 lfpm SOIC8 NB 130 Thermal Resistance (Junction-to-Case) Standard Board SOIC8 NB 41 to 44 5% C/W JC Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP8 185 C/W JA 500 lfpm TSSOP8 140 Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 5% C/W JC T Wave Solder (Pb-Free) < 2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2