3.3 V ECL 2 Divider MC100LVEL32 Description The MC100LVEL32 is an integrated 2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. www.onsemi.com Upon power-up, the internal flip-flop will attain a random state the reset allows for the synchronization of multiple LVEL32s in a system. The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused 8 8 differential input is connected to V as a switching reference voltage. 1 BB 1 V may also rebias AC coupled inputs. When used, decouple V BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC SOIC8 NB TSSOP8 to 0.5 mA. When not used, V should be left open. D SUFFIX DT SUFFIX BB CASE 75107 CASE 948R02 Features 510 ps Propagation Delay MARKING DIAGRAMS* 2.6 GHz Typical Maximum Frequency ESD Protection: 8 8 > 4 KV Human Body Model KVL32 KV32 ALYW > 200 V Machine Model ALYW The 100 Series Contains Temperature Compensation 1 1 PECL Mode Operating Range: SOIC8 NB TSSOP8 V = 3.0 V to 3.8 V with V = 0 V CC EE NECL Mode Operating Range: A = Assembly Location V = 0 V with V = 3.0 V to 3.8 V L = Wafer Lot CC EE Y = Year Internal Input Pulldown Resistors W = Work Week Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test = Pb-Free Package Moisture Sensitivity: (Note: Microdot may be in either location) Level 1 for SOIC8 *For additional marking information, refer to Level 3 for TSSOP8 Application Note AND8002/D. For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V0 0.125 in, ORDERING INFORMATION Oxygen Index: 28 to 34 Transistor Count = 111 Devices Device Package Shipping MC100LVEL32DG SOIC8 NB 98 Units / Tube These Devices are Pb-Free, Halogen Free and are RoHS Compliant (Pb-Free) MC100LVEL32DR2G SOIC8 NB 2500 / (Pb-Free) Tape & Reel MC100LVEL32DTG TSSOP8 100 Units / Tube (Pb-Free) MC100LVEL32DTR2G TSSOP8 2500 / (Pb-Free) Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2021 Rev. 12 MC100LVEL32/DMC100LVEL32 Table 1. PIN DESCRIPTION Reset 1 8 V CC Pin Function CLK*, CLK** ECL Differential Clock Inputs R Q, Q ECL Differential Data 2 Outputs CLK 2 7 Q Reset* ECL Asynch Reset V BB Reference Voltage Output 2 V Positive Supply CC V Negative Supply EE CLK 3 6 Q *Pin will default low when left open, per internal 75 K pull-down to V . EE ** Pin will default to V /2 when left open per internal 75 K pull- CC down to V and 75 K pull-up to V . EE CC V 4 5 V BB EE Figure 1. Logic Diagram and Pinout Assessment Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 to 0 V CC EE V NECL Mode Power Supply V = 0 V 8 to 0 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 to 0 CC I EE V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 to 0 CC I EE I Output Current Continuous 50 mA out Surge 100 I V Sink/Source 0.5 mA BB BB T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8 NB 190 C/W JA 500 lfpm SOIC8 NB 130 Thermal Resistance (Junction-to-Case) Standard Board SOIC8 NB 41 to 44 5% C/W JC Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP8 185 C/W JA 500 lfpm TSSOP8 140 Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 5% C/W JC T Wave Solder (Pb-Free) < 2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board 2S2P (2 signal, 2 power) www.onsemi.com 2