MC10E431, MC100E431 5 V ECL 3Bit Differential FlipFlop Description The MC10E/100E431 is a 3-bit flip-flop with differential clock, data input and data output. www.onsemi.com The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge, without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset). The E431 is also designed with larger internal swings, an approach intended to minimize the time spent crossing the threshold region and thus reduce the metastability susceptibility window. PLCC28 The differential input structures are clamped so that the inputs of FN SUFFIX unused registers can be left open without upsetting the bias network of CASE 77602 the device. The clamping action will assert the D and the CLK sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the MARKING DIAGRAM* input clamps only operate when both inputs fall to 2.5 V below V . CC 128 The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB MCxxxE431FNG V may also rebias AC coupled inputs. When used, decouple V BB BB AWLYYWW and V via a 0.01 F capacitor and limit current sourcing or sinking CC to 0.5 mA. When not used, V should be left open. BB The 100 Series contains temperature compensation. xxx = 10 or 100 Features A = Assembly Location WL = Wafer Lot Edge-Triggered Asynchronous Set and Reset YY = Year Differential D, CLK and Q V Reference Available BB WW = Work Week G = Pb-Free Package 1100 MHz Min. Toggle Frequency PECL Mode Operating Range: V = 4.2 V to 5.7 V CC *For additional marking information, refer to with V = 0 V EE Application Note AND8002/D. NECL Mode Operating Range: V = 0 V CC with V = 4.2 V to 5.7 V EE Internal Input 50 k Pulldown Resistors ORDERING INFORMATION ESD Protection: Device Package Shipping > 2 kV Human Body Model > 200 V Machine Model MC10E431FNG PLCC28 37 Units / Tube (Pb-Free) > 2 kV Charged Device Model MC10E431FNR2G PLCC28 500 Tape & Reel Meets or Exceeds JEDEC Spec EIA/JESD78 IC (Pb-Free) Latchup Test MC100E431FNR2G PLCC28 500 Tape & Reel Moisture Sensitivity: Level 3 (Pb-Free) (Pb-Free) (For Additional Information, see Application Note AND8003/D) For information on tape and reel specifications, in- Flammability Rating: UL 94 V0 0.125 in, cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Oxygen Index: 28 to 34 Brochure, BRD8011/D. Transistor Count = 348 Devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 11 MC10E431/DMC10E431, MC100E431 V CLK2 CLK2 D D R S BB 2 2 2 2 Table 1. PIN DESCRIPTION 25 24 23 22 21 20 19 PIN FUNCTION CLK1 18 Q 26 2 D 0:2 , D 0:2 ECL Differential Data Inputs CLK 0:2 , CLK 0:2 ECL Differential Clock CLK1 17 Q 27 2 S 0:2 ECL Edge Triggered Set Inputs R 16 1 28 V CC R 0:2 ECL Edge Triggered Reset Input 1 V 15 EE Q 0:2 , Q 0:2 ECL Differential Data Outputs Q 1 MC10E431/MC100E431 V Reference Voltage Output BB S 14 1 2 Q 1 V , V Positive Supply CC CCO D 13 3 1 Q 0 V Negative Supply EE D 1 4 12 Q 0 567 89 10 11 CLK0 CLK0 D D R S V 0 0 0 0 CCO * All V and V pins are tied together on the die. CC CCO Warning: All V , V , and V pins must be externally con- CC CCO EE nected to Power Supply to guarantee proper operation. Figure 1. Pinout: PLCC-28 (Top View) S 0 D S 0 D Q Q 0 Table 2. FUNCTION TABLE D 0 Dn CLKn Rn Sn Qn CLK0 Q Q 0 CLK0 R L Z L L L R 0 H Z L L H S 1 X X Z L L D S 1 D Q Q 1 D 1 X X L Z H CLK1 Z = Low to high transition Q Q 1 CLK1 R X = Dont Care R 1 S 2 D S 2 D Q Q 2 D 2 CLK2 Q Q 2 CLK2 R R 2 V BB Figure 2. Logic Diagram www.onsemi.com 2