3.3 VECL 2, 4, 8 Clock Generation Chip MC100LVEL34 Description The MC100LVEL34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. www.onsemi.com The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The V pin, an MARKING BB DIAGRAMS* internally generated voltage supply, is available to this device only. For singleended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also 16 BB BB 16 rebias AC coupled inputs. When used, decouple V and V via BB CC 100LVEL34G a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. 1 AWLYWW When not used, V should be left open. BB SOIC16 The common enable (EN) is synchronous so that the internal D SUFFIX 1 dividers will only be enabled/disabled when the internal clock is CASE 751B already in the LOW state. This avoids any chance of generating a runt 16 clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse 16 100 VL34 could lead to losing synchronization between the internal divider 1 ALYW stages. The internal enable flip-flop is clocked on the falling edge of TSSOP16 the input clock therefore, all associated specification limits are DT SUFFIX referenced to the negative edge of the clock input. 1 CASE 948F Upon startup, the internal flip-flops will attain a random state the A = Assembly Location master reset (MR) input allows for the synchronization of the internal L, WL = Wafer Lot dividers, as well as multiple LVEL34s in a system. Y = Year W, WW = Work Week Features G or = PbFree Package (Note: Microdot may be in either location) 50 ps Typical Output-to-Output Skew *For additional marking information, refer to Synchronous Enable/Disable Application Note AND8002/D. Master Reset for Synchronization 1.5 GHz Toggle Frequency ORDERING INFORMATION See detailed ordering and shipping information in the package The 100 Series Contains Temperature Compensation. dimensions section on page 7 of this data sheet. PECL Mode Operating Range: V = 3.0 V to 3.8 V with V = 0 V CC EE NECL Mode Operating Range: V = 0 V with V = 3.0 V to 3.8 V CC EE Open Input Default State LVDS Input Compatible These Devices are Pb-Free, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: March, 2021 Rev. 5 MC100LVEL34/DMC100LVEL34 Table 1. PIN DESCRIPTION PIN FUNCTION Q0 V 1 16 CC CLK*, CLK** ECL Diff Clock Inputs Q EN* ECL Sync Enable 2 Q0 EN 15 2 MR* ECL Master Reset R Q D Q0, Q0 ECL Diff 2 Outputs Q1, Q1 ECL Diff 4 Outputs V NC CC 3 14 R Q2, Q2 ECL Diff 8 Outputs V Reference Voltage Output BB Q1 CLK 4 13 V Positive Supply CC Q V Negative Supply EE 4 NC No Connect CLK Q1 12 5 * Pins will default LOW when left open. R ***Pins will default to V /2 when left open. CC V V CC BB 6 11 Table 2. FUNCTION TABLE CLK EN MR FUNCTION Q2 MR 7 10 Z L L Divide Q ZZ H L Hold Q 0 3 8 V X X H Reset Q Q2 EE 0 3 8 9 R Z = Low-to-High Transition ZZ = High-to-Low Transition Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. 16 Lead Pinout (Top View) and Logic Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 37.5 k ESD Protection Human Body Model > 2 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) PbFree Pkg SOIC16 Level 1 TSSOP16 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 210 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2