MC10E167FNR2G ON Semiconductor

MC10E167 5 V ECL 6Bit 2:1 MUXRegister Description The MC10E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the www.onsemi.com Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (MR) pin asynchronously forces all Q outputs LOW. The 100 Series contains temperature compensation. Features PLCC28 1000 MHz Min. Operating Frequency FN SUFFIX 800 ps Max. Clock to Output CASE 776 Single-Ended Outputs Asynchronous Master Resets Dual Clocks MARKING DIAGRAM* PECL Mode Operating Range: V = 4.2 V to 5.7 V CC with V = 0 V EE 1 NECL Mode Operating Range: V = 0 V CC with V = 4.2 V to 5.7 V EE Internal Input 50 k Pulldown Resistors MC10E167FNG ESD Protection: AWLYYWW > 2 kV Human Body Model > 200 V Machine Model > 2 kV Charged Device Model Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test A = Assembly Location Moisture Sensitivity: Level 3 (Pb-Free) WL = Wafer Lot YY = Year (For Additional Information, see Application Note AND8003/D) WW = Work Week Flammability Rating: UL 94 V0 0.125 in, G = Pb-Free Package Oxygen Index: 28 to 34 *For additional marking information, refer to Transistor Count = 323 Devices Application Note AND8002/D. This Device is Pb-Free, Halogen Free and is RoHS Compliant ORDERING INFORMATION Device Package Shipping PLCC8 37 Units/Tube MC10E167FNR2G (Pb-Free) Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 9 MC10E167/DMC10E167 D a Q Q 0 0 MUX D D a D b D a D b D a NC V 5 4 4 3 3 CCO D b SEL R 0 25 24 23 22 21 20 19 18 Q D a Q Q D b 26 1 5 1 5 MUX D SEL D b R 1 17 Q CLK1 27 4 Q Q D a 2 2 MUX D 28 16 CLK2 V CC SEL R D b 2 Pinout: 28-Lead PLCC 1 15 V Q EE (Top View) 3 D a Q 3 Q 3 MUX D 2 14 Q MR 2 SEL D b R 3 3 13 D a V SEL 4 CCO Q Q 4 MUX D SEL R D b 4 4 D a 12 Q 0 1 D a 5 Q Q 5 D MUX 56 7 8 9 10 11 SEL D b R 5 DbDaDbDaDbV Q 0 1 1 2 2 CCO 0 SEL * All V and V pins are tied together on the die. CC CCO CLK1 CLK2 Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. MR Figure 2. Logic Diagram Figure 1. 28-Lead Pinout Assignment Table 1. PIN DESCRIPTION PIN FUNCTION D a D a ECL Input Data a 0 5 D b D b ECL Input Data b 0 5 SEL ECL Select Input CLK1, CLK2 ECL Clock Inputs MR ECL Master Reset Q Q ECL Data Outputs 0 5 V , V Positive Supply CC CCO V Negative Supply EE NC No Connect Table 2. FUNCTION TABLE SEL Data H a L b www.onsemi.com 2