MC10E143, MC100E143 5 VECL 9Bit Hold Register Description The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 D8 accepting parallel input data. www.onsemi.com The SEL (Select) input pin is used to switch between the two modes of operation HOLD and LOAD. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero. The 100 Series contains temperature compensation. Features PLCC28 700 MHz Min. Operating Frequency FN SUFFIX CASE 77602 9-Bit for Byte-Parity Applications Asynchronous Master Reset Dual Clocks PECL Mode Operating Range: MARKING DIAGRAM* V = 4.2 V to 5.7 V with V = 0 V CC EE 1 NECL Mode Operating Range: V = 0 V with V = 4.2 V to 5.7 V CC EE Internal Input 50 k Pulldown Resistors MCxxxE143FNG AWLYYWW ESD Protection: Human Body Model > 2 kV Machine Model > 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test xxx = 10 or 100 Moisture Sensitivity Level: 3 (Pb-Free) A = Assembly Location WL = Wafer Lot For Additional Information, see Application Note AND8003/D YY = Year Flammability Rating: UL 94 V0 0.125 in, WW = Work Week Oxygen Index: 28 to 34 G = Pb-Free Package Transistor Count = 484 devices *For additional marking information, refer to Application Note AND8002/D. These Devices are Pb-Free, Halogen Free and are RoHS Compliant ORDERING INFORMATION Device Package Shipping MC10E143FNR2G PLCC28 500/Tape & Reel (Pb-Free) MC100E143FNG PLCC28 37 Units/Tube (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 8 MC10E143/DMC10E143, MC100E143 SEL D D D D V Q 8 7 6 5 CCO 8 D Q 0 MUX 25 24 23 22 21 20 19 D 0 R MR 26 18 Q 7 Q D 1 CLK1 27 17 Q MUX 6 D R 1 CLK2 28 16 V CC D Q 2 MUX 1 V D 15 R EE Q 2 Pinout: 28-Lead PLCC 5 (Top View) NC 2 14 V CCO Q D 3 MUX R D 3 D 3 13 0 Q 4 D 1 4 12 Q 3 567 89 10 11 D D D V Q Q Q Q 2 3 4 CCO 0 1 2 D 8 MUX R D 8 * All V and V pins are tied together on the die. CC CCO Warning: All V , V , and V pins must be externally CC CCO EE SEL connected to Power Supply to guarantee proper operation. CLK1 CLK2 Figure 1. 28-Lead Pinout MR Figure 2. Logic Diagram Table 1. PIN DESCRIPTION PIN FUNCTION D D ECL Parallel Data Inputs 0 8 SEL ECL Mode Select Input CLK1, CLK2 ECL Clock Inputs MR ECL Master Reset Q Q ECL Data Outputs 0 8 NC No Connect V , V Positive Supply* CC CCO V Negative Supply EE *From V pin to each V pin is an internal 100 resistor. CC CCO Table 2. FUNCTIONS SEL Mode L Load H Hold www.onsemi.com 2