MC10EP29, MC100EP29
3.3V / 5VECL Dual
Differential Data and Clock
D Flip-Flop With Set and
Reset
MC10EP29, MC100EP29
V R0 S0 Q0 Q0 Q1 Q1 S1 R1 V
CC EE
20 19 18 17 16 15 14 13 12 11
R S Q
Q S R
Q Q
CLK D
D CLK
1 2354 678 9 10
D0 D0 V CLK0 CLK0 CLK1 CLK1 D1 D1 V
BB CC
Warning: All V and V pins must be externally connected
CC EE
to Power Supply to guarantee proper operation.
Figure 1. 20Lead Pinout (Top View) and Logic Diagram
Exposed Pad
D0 D0 V R0 S0
CC
20 19 18 17 16
1 15
V Q0
BB
2 14
CLK0 Q0
MC10/100EP29
3 13
CLK0 Q1
4
12
CLK1 Q1
5
11
CLK1 S1
67 8 9 10
D1 D1 V V R1
CC EE
NOTE: The Exposed Pad (EP) on package bottom must be attached to a heatsinking conduit.
The Exposed Pad may only be electrically connected to V .
EE
Figure 1. QFN20 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Function
Table 2. TRUTH TABLE
D0*, D0*; D1*, D1* ECL Differential Data Inputs
R S D CLK Q Q
R0*, R1* ECL Reset Inputs
L L L Z L H
CLK0*, CLK0* ECL Differential Clock Inputs
L L H Z H L
CLK1*, CLK1* ECL Differential Clock Inputs
H L X X L H
S0* S1* ECL Set Inputs
L H X X H L
Q0, Q0; Q1, Q1 ECL Differential Data Outputs
H H X X Undef Undef
V Reference Voltage Output
BB
Z = LOW to HIGH Transition
X = Dont Care
V Positive Supply
CC
V Negative Supply
EE
EP Exposed Pad
*Pins will default LOW when left open.