MC100EP32D ON Semiconductor

MC10EP32, MC100EP32 3.3V / 5VECL 2 Divider Description The MC10/100EP32 is an integrated 2 divider with differential CLK inputs. The V pin, an internally generated voltage supply, is available to BB MC10EP32, MC100EP32 Table 1. PIN DESCRIPTION RESET 1 8 V CC Pin Function R CLK, CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset CLK 2 7 Q V Reference Voltage Output BB 2 Q, Q ECL Data Outputs V Positive Supply CLK 3 6 Q CC V Negative Supply EE EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal con- V45 V BB EE duit. Electrically connect to the most neg- ative supply (GND) or leave unconnec- ted, floating open. Figure 1. 8Lead Pinout (Top View) and Logic *Pins will default LOW when left open. Diagram Table 2. TRUTH TABLE CLK CLK RESET Q Q X X Z L H Z Z L F F Z = LOW to HIGH Transition Z = HIGH to LOW Transition F = Divide by 2 Function CLK t RR RESET Q Figure 2. Timing Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg PbFree Pkg SOIC8 Level 1 Level 1 TSSOP8 Level 1 Level 3 DFN8 Level 1 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 78 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.