3.3 V/5 VECL 4 Divider MC10EP33, MC100EP33 Description The MC10/100EP33 is an integrated 4 divider. The differential clock inputs. The V pin, an internally generated voltage supply, is available to BB www.onsemi.com this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC 8 8 to 0.5 mA. When not used, V should be left open. BB 1 1 The reset pin is asynchronous and is asserted on the rising edge. Upon powerup, the internal flip-flops will attain a random state the SOIC8 NB TSSOP8 DFN8 reset allows for the synchronization of multiple EP33s in a system. D SUFFIX DT SUFFIX MN SUFFIX The 100 Series contains temperature compensation. CASE 75107 CASE 948R02 CASE 506AA Features 320 ps Propagation Delay Maximum Frequency = > 4 GHz Typical MARKING DIAGRAMS* PECL Mode Operating Range: 8 V = 3.0 V to 5.5 V with V = 0 V 8 CC EE HEP33 NECL Mode Operating Range: HP33 ALYW ALYW V = 0 V with V = 3.0 V to 5.5 V CC EE Open Input Default State 1 1 Safety Clamp on Inputs 8 8 Q Output Will Default LOW with Inputs Open or at V EE KEP33 KP33 V Output ALYW BB ALYW These Devices are Pb-Free, Halogen Free and are RoHS Compliant 14 1 1 SOIC8 NB TSSOP8 DFN8 H = MC10 A = Assembly Location K = MC100 L = Wafer Lot Y = Year W = Work Week 3L = MC100 M = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: June, 2021 Rev. 12 MC10EP33/D 3L M MC10EP33, MC100EP33 Table 1. PIN DESCRIPTION PIN FUNCTION RESET 1 8 V CLK*, CLK* ECL Clock Inputs CC R Reset* ECL Asynchronous Reset V Reference Voltage Output BB CLK 2 7 Q Q, Q ECL Data Outputs 4 V Positive Supply CC V Negative Supply EE CLK 3 6 Q EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal con- duit. Electrically connect to the most neg- ative supply (GND) or leave unconnected, V45 V BB EE floating open. * Pins will default LOW when left open. Table 2. TRUTH TABLE Figure 1. 8-Lead Pinout (Top View) and Logic Diagram CLK CLK RESET Q Q X X Z L H Z Z L F F Z = LOW to HIGH Transition Z = HIGH to LOW Transition F = Divide by 4 Function CLK t RR RESET Q Figure 2. Timing Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor NA ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8 NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating UL94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 91 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2