NB3N3020DTG ON Semiconductor

NB3N3020 3.3 V, LVPECL/LVCMOS Clock Multiplier Description The NB3N3020 is a high precision, low phase noise selectable clock multiplier. The device takes a 5 27 MHz fundamental mode parallel NB3N3020 OE2 GND VDD 527 MHz Crystal or 2 210 MHz Clock X1/CLK CLK2 Clock Pre Phase LVPECL Loop Filter VCO Buffer/ Sca Detector Output ler Crystal CLK2 Oscillator X2 LVCMOS/ CLK1 LVTTL %N Output Select Control Block Sel0 Sel1 Sel2 OE1 Figure 1. NB3N3020 Simplified Logic Diagram Table 1. PIN DESCRIPTION Pin Name I/O Description 6 Sel0 TriLevel Input Frequency select input 0. When left open, defaults to VDD/ 2. See output select Table 2 for details. 5 Sel1 TriLevel Input Frequency select input 1. When left open, defaults to VDD/ 2. See output select Table 2 for details. 4 Sel2 TriLevel Input Frequency select input 2. When left open, defaults to VDD/ 2. See output select Table 2 for details. 1, 11, 15 V Power Supply Positive supply voltage pins are connected to +3.3 V supply voltage. DD 2 X1/CLK Input Crystal or Clock input. Connect to 5 27 MHz crystal source or 2 210 MHz single ended clock. See Table 2. 3 X2 Input Crystal input. Connect to a 5 27 MHz crystal or leave unconnected for clock input. See Table 2. 7 OE1 LVTTL/LVCMOS Output enable input that synchronously tri states CLK1 output when low. Internal pullup Input resistor to V . DD 16 OE2 LVTTL/LVCMOS Output enable input that when LOW synchronously controls LVPECL outputs by forcing Input CLK2 LOW and CLK2 HIGH. Internal pullup resistor to V . DD 8, 9, 12 GND Power Supply Ground 0 V. These pins provide GND return path for the devices. 13 CLK2 LVPECL Output Inverted clock output. Clock frequency equals input frequency times multiplier. 14 CLK2 LVPECL Output Noninverted clock output. Clock frequency equals input frequency times multiplier. 10 CLK1 LVTTL/ LVCMOS Clock Output. Clock frequency equals input frequency times multiplier. Output