NB3N501 3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier Description NB3N501 Table 1. CLOCK MULTIPLIER SELECT TABLE X1/CLK 1 8 X2 S1* S0* CLKOUT Multiplier L L 4X Input V DD 2 7 OE L M 5.3125X Input GND 3 L H 5X Input 6 S0 M L 6.25X Input S145 CLKOUT M M 2X Input M H 3.125X Input H L 6X Input Figure 2. NB3N501 Package Pinout, 8Pin (150 mil) SOIC H M 3X Input H H 8X Input *Pins S1 and S0 default to M when open L = GND H = VDD M = OPEN (unconnected will default to VDD/2) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 X1/CLK Input Crystal or external reference clock input 2 VDD Power supply Positive supply voltage 3 GND Power supply 0 V. Ground. 4 S1 Three level Input Multiplier select pin connect to V , GND or float DD 5 CLKOUT CMOS/TTL Output Clock output 6 S0 Three level Input Multiplier select pin connect to V , GND or float DD 7 OE CMOS/TTL Input Output Enable. CLKOUT is high impedance when OE is low. Internal pullup 8 X2 Crystal Crystal input Leave open when providing an external clock reference Table 3. COMMON OUTPUT FREQUENCY Table 3. COMMON OUTPUT FREQUENCY EXAMPLES EXAMPLES Output Frequency Input Frequency Output Frequency Input Frequency (MHz) (MHz) (MHz) (MHz) S1, S0 S1, S0 64 16 0, 0 20 10 M, M 66.66 16.66 0, 0 24 12 M, M 72 12 1, 0 30 10 1, M 75 12 M, 0 32 16 M, M 80 10 1, 1 33.33 16.66 M, M 83.33 16.66 0, 1 37.5 12 M, 1 90 15 1, 0 40 10 0, 0 100 20 0, 1 48 12 0, 0 106.25 20 0, M 50 16.66 1, M 120 15 1, 1 60 10 1, 0 125 20 M, 0 62.5 20 M, 1