NB3N401S 3.3 V Quad Channel HalfDuplex M-LVDS Driver Receiver Description The NB3N401S is a 3.3 V supply Quad Multipoint Low Voltage www.onsemi.com Differential Signals (MLVDS) line drivers and receivers. The device is TIA/EIA899 compliant. The device offers the Type 1 receiver threshold at 0.0V and the Type2 receiver threshold at 0.1V. TheNB3N401S supports four independent Half Duplex bus configurations. Each of the four sections has Pin (SEL) for selection of Type1 and 148 Type2 receivers that detect the bus state with as little as 50 mV of QFN48 differential input voltage over a common mode voltage range of 1 V CASE 485EP to 3.4 V. The Type1 receivers have near zero thresholds (50 mV) and exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. MARKING DIAGRAM Type2 receivers include an offset threshold to provide a detectable 1 voltage under open-circuit, idle-bus, and other faults conditions. The NB3N401S is offered in a 48 Pin 7 mm 7mm 0.9 mm QFN NB3N401S package. AWLYYWWG Features Low-Voltage Differential 30 to 55 Line Drivers and Receivers for Signaling Rates Up to 250 Mbps NB3N401S = Specific Device Code A = Assembly Location Clock Frequencies up to 125 MHz WL = Wafer Lot Type1 Receivers Incorporate 25 mV of Hysteresis YY = Year Type2 Receivers Provide an Offset (100 mV) WW = Work Week G = PbFree Package Compatible with TIA/EIA899 Standard for Multipoint Data Interchange LOGIC DIAGRAM Controlled Driver Output Voltage Transition Times for Improved Signal Quality DE1 1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer A1 D1 With up to 2 V of Ground Noise B1 Bus Pins High Impedance when Disabled or V 1.5 V CC SEL1 Independent Enable for each Driver and Receiver R1 Independent Select for each Type1 and Type2 Receivers RE1 Channel 1 PDN MLVDS Bus Power Up/Down Glitch Free Power Down Pin for Device Power Down DE2DE4 A2A4 Operating Range: V = 3.3 V 0.3 V (3.0 to 3.6 V) CC D2D4 B2B4 Channel 24 Operation from 40C to 85C. RE2RE4 R2R4 Enhanced ESD Protection: 7 kV HBM on all the Pins SEL2SEL4 These are Pb-Free Devices Applications Mobile Base Station Back Plane System ORDERING INFORMATION Central Office Switches See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. Network Switches Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: November, 2016 Rev. 0 NB3N401S/DNB3N401S 48 47 46 45 44 43 42 41 40 39 38 37 1 36 R1 DE1 2 35 D1 VCC A2 3 34 GND 4 33 R2 B2 DE2 5 32 D2 GND 6 31 GND QFN48 (7 mm 7 mm 0.9 mm) GND 7 30 PDN DE3 8 29 R3 A3 9 28 D3 10 27 GND B3 11 26 R4 VCC 12 25 D4 DE4 13 15 17 19 21 23 14 16 18 20 22 24 Figure 1. Pinout Diagram (Top View) Table 1. PIN DESCRIPTION Number Name I/O Type Description 1, 5, 8, 12 DE1DE4 INPUT Driver Enable Pins Separate for each Driver, (HIGH = Active, LOW = High Z Output). This Pin will be pulled internally to Logic LOW when left open 2, 11, 15, 16, VCC Power Supply Pins. Pins must be connected to power supply to guarantee 24, 37, 45, 46 proper operations 3, 9, 13, 47 A1A4 MLVDS Input/Output Transceiver Input/Output Pins 4, 10, 14, 48 B1B4 MLVDS Input/Output Transceiver Invert Input/Output Pins 6, 7, 18, 23, 27, GND Ground Pins. All pins must be connected to Ground to guarantee proper 31, 34, 38, 43 operations 19, 21, 40, 42 RE1RE4 INPUT Receiver Enable Pins Separate for each Receiver, (LOW = Active, HIGH = High Z Output). This Pin will be pulled internally to Logic HIGH when left open 20, 22, 39, 41 SEL1SEL4 INPUT Failsafe Enable Pins. Separate for each Receiver section. LOW = Type 1 Receiver Input, HIGH = Type 2 Receiver Input. This Pin will be pulled internally to Logic HIGH when left open 25, 28, 32, 35 D1D4 LVCMOS INPUT Driver Input Pins 26, 29, 33, 36 R1R4 LVCMOS OUTPUT Receiver Output Pins 30 PDN INPUT Power Down Pin. When pulled Low, Device powers down. (HIGH = Active, LOW = High Z Output). This Pin will be pulled internally to Logic LOW when left open. GNDPAD Exposed PAD Must be connected to GND on the PCB for proper device operation 17, 44 NC No Connect (Pins must be left open) www.onsemi.com 2 A4 B1 B4 A1 VCC VCC VCC VCC NC NC GND GND RE3 RE2 SEL3 SEL2 RE4 RE1 SEL4 SEL1 GND GND VCC VCC