14 MHz to 190 MHz PLL Clock Multiplier NB3N502 Description The NB3N502 is a clock multiplier device that generates a low jitter, www.onsemi.com TTL/CMOS level output clock which is a precise multiple of the external input reference clock signal source. The device is a cost efficient replacement for the crystal oscillators commonly used in MARKING DIAGRAM electronic systems. It accepts a standard fundamental mode crystal or an external reference clock signal. PhaseLockedLoop (PLL) design 8 8 techniques are used to produce an output clock up to 190 MHz with a 1 3N502 50% duty cycle. The NB3N502 can be programmed via two select ALYW SOIC8 inputs (S0, S1) to provide an output clock (CLKOUT) at one of six D SUFFIX 1 different multiples of the input frequency source, and at the same time CASE 751 output the input aligned reference clock signal (REF). 3N502 = Specific Device Code A = Assembly Location Features L = Wafer Lot Clock Output Frequency up to 190 MHz Y = Year W = Work Week Operating Range: V = 3 V to 5.5 V DD = PbFree Package Low Jitter Output of 15 ps One Sigma (rms) Zero ppm Clock Multiplication Error ORDERING INFORMATION 45% 55% Duty Cycle Device Package Shipping 25 mA TTLlevel Drive Outputs NB3N502DG SOIC8 98 Units / Rail Crystal Reference Input Range of 5 27 MHz (PbFree) Input Clock Frequency Range of 2 50 MHz NB3N502DR2G SOIC8 3000 / Tape & Reel Available in 8pin SOIC Package or in Die Form (PbFree) Full Industrial Temperature Range 40C to 85C For information on tape and reel specifications, These are PbFree Devices including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. V DD TTL/ Reference CMOS REF Clock Output X1/CLK Crystal TTL/ P Phase Charge Oscillator CMOS CLKOUT VCO X2 Pump Detector Output Multiplier Select Feedback M S1 S0 GND Figure 1. NB3N502 Logic Diagram Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: November, 2019 Rev. 2 NB3N502/DNB3N502 X1/CLK 1 8 X2 V DD 2 7 S1 3 GND 6 S0 REF 45 CLKOUT Figure 2. Pin Configuration (Top View) Table 1. CLOCK MULTIPLIER SELECT TABLE S1* S0** Multiplier L L 2X L = GND H = V L H 5X DD M = OPEN (unconnected) M L 3X * Pin S1 defaults to M when left open M H 3.33X ** Pin S0 defaults to H when left open H L 4X H H 2.5X Table 2. OUTPUT FREQUENCY EXAMPLES Output Frequency (MHz) 20 25 33.3 48 50 54 64 66.66 75 100 108 120 135 Input Frequency (MHz) 10 10 10 16 20 13.5 16 20 15 20 27 24 27 S1, S0 0 ,0 1, 1 M, 1 M, 0 1, 1 1, 0 1, 0 M, 1 0, 1 0, 1 1, 0 0, 1 0, 1 Table 3. PIN DESCRIPTION Pin Name I/O Description 1 X1/CLK Input Crystal or External Reference Clock Input 2 V Power Supply Positive Supply Voltage (3 V to 5.5 V) DD 3 GND Power Supply 0 V Ground. 4 REF CMOS/TTL Output Buffered Crystal Oscillator Clock Output 5 CLKOUT CMOS/TTL Output Clock Output 6 S0 CMOS/TTL Input Multiplier Select Pin Connect to V or GND. Internal Pullup Resistor. DD 7 S1 Threelevel Input Multiplier Select Pin Connect to V , GND or Float to M. DD 8 X2 Crystal Input Crystal Input Do Not Connect when Providing an External Clock Reference Table 4. ATTRIBUTES Characteristic Value ESD Protection Human Body Model > 8 kV Machine Model > 600 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 6700 Devices Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. www.onsemi.com 2