NB3N5573 Clock Generator, Crystal to 25 MHz, 100 MHz, 125 MHz, 200 MHz, 3.3 V, with Dual HCSL www.onsemi.com Description The NB3N5573 is a precision, low phase noise clock generator that MARKING supports PCI Express and Ethernet requirements. The device accepts a DIAGRAM 25 MHz fundamental mode parallel resonant crystal and generates a 16 16 differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz NB3N clock frequencies. Outputs can interface with LVDS with proper 1 5573 termination (See Figure 4). ALYW TSSOP16 This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16 DT SUFFIX 1 pin package. CASE 948F Features A = Assembly Location L = Wafer Lot Uses 25 MHz Fundamental Mode Parallel Resonant Crystal Y = Year External Loop Filter is Not Required W = Work Week HCSL Differential Output or LVDS with Proper Termination = PbFree Package Four Selectable Multipliers of the Input Frequency (Note: Microdot may be in either location) Output Enable with TriState Outputs PCIe Gen1, Gen2, Gen3, Gen4, QPI, UPI Jitter Compliant ORDERING INFORMATION Phase Noise: 100 MHz See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Offset Noise Power 100 Hz 109.4 dBc 1 kHz 127.8 dBc 10 kHz 136.2 dBc 100 kHz 138.8 dBc 1 MHz 138.2 dBc 10 MHz 161.4 dBc 20 MHz 163.00 dBc Typical Period Jitter RMS of 1.5 ps Operating Range 3.3 V 10% Industrial Temperature Range 40C to +85C These are PbFree Devices VDD X1/CLK CLK0 Clock Buffer Phase Charge HSCL VCO 25 MHz Clock or Crystal Oscillator Detector Pump Output Crystal X2 CLK0 HSCL CLK1 M Output CLK1 GND S0 S1 OE IREF Figure 1. NB3N5573 Simplified Logic Diagram Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: November, 2018 Rev. 12 NB3N5573/DNB3N5573 S0 1 16 VDD S1 2 15 CLK0 NC 3 14 CLK0 X1/CLK 4 13 GND X2 5 12 VDD OE 6 11 CLK1 GND 7 10 CLK1 NC 8 9 IREF Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Symbol I/O Description 1 S0 Input LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to V . See output select DD table 2 for details. 2 S1 Input LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to V . See output select DD Table 2 for details. 12, 16 V Power Supply Positive supply voltage pins are connected to +3.3 V supply voltage. DD 4 X1/CLK Input Crystal or Clock input. Connect to 25 MHz crystal source or singleended clock. 5 X2 Input Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input. 6 OE Input Output enable tristates output when connected to GND. Internal pullup resistor to V . DD 7, 13 GND Power Supply Ground 0 V. These pins provide GND return path for the devices. 9 I Output Output current reference pin. Precision resistor (typ. 475 ) is connected to set the output REF current. 11 CLK1 HCSL or Noninverted clock output. (For LVDS levels see Figure 4) LVDS Output 10 CLK1 HCSL or Inverted clock output. (For LVDS levels see Figure 4) LVDS Output 15 CLK0 HCSL or Noninverted clock output. (For LVDS levels see Figure 4) LVDS Output 14 CLK0 HCSL or Inverted clock output. (For LVDS levels see Figure 4) LVDS Output 3, 8 NC Do not connect Recommended Crystal Parameters Table 2. OUTPUT FREQUENCY SELECT TABLE WITH 25MHz CRYSTAL Crystal Fundamental ATCut Frequency 25 MHz S1* S0* CLK Multiplier f (MHz) CLKout Load Capacitance 1620 pF L L 1x 25 Shunt Capacitance, C0 7 pF Max L H 4x 100 Equivalent Series Resistance 50 Max Initial Accuracy at 25 C 20 ppm H L 5x 125 Temperature Stability 30 ppm H H 8x 200 Aging 20 ppm *Pins S1 and S0 default high when left open. Drive Level 100 W Max www.onsemi.com 2