3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer NB3N853531E www.onsemi.com Description The NB3N853531E is a low skew 3.3 V supply 1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by using the CLK SEL pin (HIGH for Crystal, LOW for Clock) with LVCMOS / LVTTL levels. TSSOP20 DT SUFFIX The single ended CLK input is translated to four LVPECL Outputs. CASE 948E Using the crystal input, the NB3N853531E can be a Clock Generator. A CLK EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable MARKING DIAGRAM outputs, LOW to disable outputs). Features NB3N Four Differential 3.3 V LVPECL Outputs 531E ALYW Selectable Crystal or LVCMOS/LVTTL CLOCK Inputs Up to 266 MHz Clock Operation Output to Output Skew: 30 ps (Max) A = Assembly Location Device to Device Skew 200 ps (Max) L = Wafer Lot Propagation Delay 1.8 ns (Max) Y = Year W = Work Week Operating Range: V = 3.3 5% V( 3.135 to 3.465 V) CC = PbFree Package Additive Phase Jitter, RMS: 0.053 ps (Typ) (Note: Microdot may be in either location) Synchronous Clock Enable Control Industrial Temp. Range (40C to 85C) ORDERING INFORMATION PbFree TSSOP20 Package Device Package Shipping Ambient Operating Temperature Range 40C to +85C NB3N853531EDTR2G TSSOP20 2500 / These Devices are PbFree and are RoHs Compliant (PbFree) Tape & Reel Pullup For information on tape and reel specifications, CLK EN D including part orientation and tape sizes, please Q Q0 refer to our Tape and Reel Packaging Specification Q0 Brochure, BRD8011/D. Pulldown CLK 0 Q1 XTAL IN Q1 1 OSC XTAL OUT Q2 Q2 Pulldown CLK SEL Q3 Q3 Figure 1. Simplified Logic Diagram Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: May, 2021 Rev. 7 NB3N853531E/DNB3N853531E V 1 20 Q0 EE CLK EN 2 19 Q0 CLK SEL 3 18 V CC 17 Q1 4 CLK 16 Q1 nc 5 XTAL IN 15 6 Q2 XTAL OUT 14 7 Q2 nc 13 8 V CC nc 12 Q3 9 V 11 Q3 CC 10 Figure 2. Pinout Diagram (Top View) Table 1. PIN DESCRIPTION Open Default Pin Name I/O Description 1 V Negative (Ground) Power Supply pin must be externally connected to EE power supply to guarantee proper operation. 2 CLK EN LVCMOS / Pullup Synchronized Clock Enable when HIGH. When LOW, outputs are LVTTL disabled (Qx HIGH, Qx LOW) 3 CLK SEL LVCMOS / Pulldown Clock Input Select (HIGH selects crystal, LOW selects CLK input) LVTTL 4 CLK LVCMOS / Pulldown Clock Input. Float open when unused. LVTTL 5, 8, 9 nc No Connect 6 XTAL IN Crystal Crystal Oscillator Input (used with pin 7). Float open when unused. 7 XTAL OUT Crystal Crystal Oscillator Output (used with pin 6). Float open when unused. 10, 13, 18 V Positive Power Supply pins must be externally connected to power CC supply to guarantee proper operation. 11, 14, 16, Q 3:0 LVPECL Complement Differential Outputs (See AND8002/D for termination) 19 12, 15, 17, Q 3:0 LVPECL True Differential Outputs (See AND8002/D for termination) 20 Table 2. FUNCTIONS Inputs Outputs CLK EN CLK SEL Input Function Output Function Qx Qx 0 0 CLK input selected Disabled LOW HIGH 0 1 Crystal Inputs Selected Disabled LOW HIGH 1 0 CLK input selected Enabled CLK0 Invert of CLK1 1 1 Crystal Inputs Selected Enabled CLK1 Invert of CLK1 1. After CLK EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3. www.onsemi.com 2