NB3N65027DTR2G ON Semiconductor

NB3N65027 3.3V Programmable 3-PLL Clock Synthesizer with 6 LVTTL/LVCMOS Outputs w/OE The NB3N65027 is a LVCMOS PLLsynthesized clock generator. It accepts a 10 MHz to 27 MHz clock or fundamental mode crystal as the reference source and drives three independent, low noise NB3N65027 1 ACS0 20 BCS1 2 X2 19 BCS0 X1/ICLK 3 18 REFOUT VDD 4 17 CLKA1 16 ACS1 5 VDD GND 6 15 OE CLKC1 7 14 GND CLKC2 8 13 CLKA2 CLKB2 9 12 NC CLKB1 10 11 CCS Figure 2. Pinout: QSOP20 (Top View) Table 1. PIN DESCRIPTION (Note 1) Pin Number Pin Name Pin Type Pin Description 1 ACS0 TriLevel Input A Clock Select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3. 2 X2 Input Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock input. 3 X1/ICLK Input Crystal or Clock input connection. If a clock input is used, drive it into X1 and leave X2 unconnected. 4 VDD Power Connect to +3.3 V. Must be the same as pin 16. 5 ACS1 TwoLevel Input A Clock Select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal pull up. 6 GND Power Connect to ground. 7 CLKC1 Output Output Clock C1. Depends on setting of CCS per table on page 3. 8 CLKC2 Output Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1. 9 CLKB2 Output Output Clock B2. Depends on setting of BCS1, 0 per table on page 3. 10 CLKB1 Output Output Clock B1. Depends on setting of BCS1, 0 per table on page 3. 11 CCS TriLevel Input Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3. 12 NC No Connect 13 CLKA2 Output Output Clock A2. Depends on setting of ACS1, 0 per table on page 3. 14 GND Power Connect to ground. 15 OE Input Output enable. Tristates all outputs when low. Internal pullup. 16 VDD Power Connect to +3.3 V. Must be the same as pin 4. 17 CLKA1 Output Output Clock A1. Depends on setting of ACS1, 0 per table on page 3. 18 REFOUT Output Buffered reference clock output. Same frequency as crystal or clock input. 19 BCS0 TriLevel Input B Clock Select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3. 20 BCS1 TwoLevel Input B Clock Select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal pull up. 1. All VDD and GND pins must be externally connected to a power supply for proper operation.