NB3N65027DTGEVB NB3N65027 Evaluation Board User s Manual NB3N65027DTGEVB Figure 3. Evaluation Board top Figure 4. Evaluation Board View (Bare PCB) bottom View (Bare PCB) The Schematic of the Evaluation board is shown in The state of signal Output Enable (OE) is controlled Figure 5. The bill of material for the Evaluation board is through 3pin through hole header OE. shown in Table 1. The state of control pins ACS0, ACS1, BCS0, BCS1 and CCS are controlled through 3pin through hole headers of Test and Measurement Setup and Procedure the same name. The selected states of the signals determine Power supply is fed to the board through VDD and GND the output clocks on CLKA1, CLKA2, CLKB1, CLKB2, terminals. C6, C7, and C8 are the decoupling capacitors for CLKC1, and CLKC2 as per the clock selection table. the power supply into the board. Decoupling capacitors C1 Output clocks REFOUT, CLKA1, CLKA2, CLKB1, and C2 are provided close to the device on VDD1, while C3 CLKB2, CLKC1, and CLKC2 can be monitored at 2pin and C4 are provided close to device on VDD2 respectively. through hole headers REFOUT, CLKA1, CLKA2, CLKB1, Crystal Y1, capacitors C5 and C9 provide the crystal CLKB2, CLKC1, and CLKC2 respectively, provided close interface to the device at X1 and X2. The values of C5 and to device. C9 are chosen based on the load capacitance (CL) of the Resistors R1 ~ R7 are the Series terminating resistors on crystal used. When Crystal interface is used, XIN, R9 and the output clocks. R10 are not mounted. The general performance of NB3N65027 on the When crystal interface is not used, clock can be fed from evaluation board can be tested using the list of instruments an external source using XIN and R10. R9 is used for output mentioned in the manual. termination of the clock source.