NB3N853501E 3.3 V LVTTL/LVCMOS 2:1 MUX to 4 LVPECL Differential Clock Fanout Buffer Outputs with Clock NB3N853501E V 1 20 Q0 EE CLK EN 2 19 Q0 CLK SEL 3 18 V CC 4 17 Q1 CLK0 16 Q1 nc 5 CLK1 15 6 Q2 nc 14 7 Q2 nc 13 8 V CC nc 12 Q3 9 V 11 Q3 CC 10 Figure 2. Pinout Diagram (Top View) Table 1. PIN DESCRIPTION Open Default Number Name I/O Description 1 V Negative (Ground) Power Supply pin must be externally connected to EE power supply to guarantee proper operation. 2 CLK EN LVCMOS / Pullup Synchronized Clock Enable when HIGH. When LOW, outputs are LVTTL disabled (Qx HIGH, Qx LOW) 3 CLK SEL LVCMOS / Pulldown Clock Input Select (HIGH selects CLK1, LOW selects CLK0 input) LVTTL 4 CLK0 LVCMOS / Pulldown Clock 0 Input. Float open when unused. LVTTL 5, 6, 8, 9 nc No Connect 6 CLK1 LVCMOS / Pulldown Clock 1 Input. Float open when unused. LVTTL 10, 13, 18 V Positive Power Supply pins must be externally connected to power CC supply to guarantee proper operation. 11, 14, 16, Q 3:0 LVPECL Invert Differential Outputs 19 12, 15, 16, Q 3:0 LVPECL True Differential Outputs 20 Table 2. FUNCTIONS Inputs Outputs CLK EN CLK SEL Input Function Output Function Qx Qx 0 0 CLK0 input selected Disabled LOW HIGH 0 1 CLK1 Input Selected Disabled LOW HIGH 1 0 CLK0 input selected Enabled CLK0 Invert of CLK1 1 1 CLK1 Input Selected Enabled CLK1 Invert of CLK1 1. After CLK EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.