NB3RL02FCT2G ON Semiconductor

NB3RL02 Low Phase-Noise Two-Channel Clock Fanout Buffer The NB3RL02 is a lowskew, low jitter 1:2 clock fanout buffer, ideal for use in portable endequipment, such as mobile phones. With www.onsemi.com integrated LDO and output control circuitry. The MCLK IN pin has an AC coupling capacitor and will directly MARKING accept a square or sine wave clock input, such as a temperature DIAGRAMS compensated crystal oscillator (TCXO). The minimum acceptable input amplitude of the sine wave is 300 mV peaktopeak. WLCSP8 RLYYWW The two clock outputs are enabled by control inputs CLK REQ1 CASE 499BQ and CLK REQ2. The NB3RL02 has an integrated LowDrop Out (LDO) voltage regulator which accepts input voltages from 2.3 V to 5.5 V and outputs RL = Specific Device Code 1.8 V at I = 50 mA. This 1.8 V supply is externally available to out YY = Year provide regulated power to peripheral devices, such as a TCXO. WW = Work Week The adaptive clock output buffers offer controlled slewrate over a = PbFree Package wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines. The NB3RL02 is offered in a 0.4 mm pitch waferlevelchipscale LOGIC DIAGRAM (WLCS) package and is optimized for very low standby current consumption. Features Low Additive Noise: 149 dBc/Hz at 10 kHz Offset Phase Noise 0.37 ps (rms) Output Jitter Limited Output Slew Rate for EMI Reduction (1 ns to 5 ns/Rise/Fall Time for 1050 pF Loads) Regulated 1.8 V Output Supply Available for External Clock Source, ie. TCX0 Operation to 80 MHz ORDERING INFORMATION UltraSmall Package: See detailed ordering and shipping information in the package 8ball: 0.4 mm Pitch WLCS dimensions section on page 6 of this data sheet. ESD Performance Exceeds JESD 22 2000 V HumanBody Model (A114A) 200 V Machine Model (A115A) 1000 V ChargedDevice Model (JESD22C101A Level III) These are PbFree Devices Applications Cellular Phones Global Positioning Systems (GPS) Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: August, 2019 Rev. 6 NB3RL02/DNB3RL02 12 A1 A2 A B1 B2 B C1 C2 C D1 D2 D (Package Flip Chip) Die Pads Face Down on PCB Figure 1. Pinout (Top View) Table 1. PIN DESCRIPTION Ball No. Name I/O Description A1 VBATT I Input to internal LDO A2 CLK OUT1 O Clock output 1 B1 VLDO O 1.8 V supply for NB3RL02 and external TCXO B2 CLK REQ1 I Clock request from peripheral 1 C1 MCLK IN I Master clock input C2 CLK REQ2 I Clock request from peripheral 2 D1 GND Ground D2 CLK OUT2 O Clock output 2 Table 2. FUNCTION TABLE Inputs Outputs CLK REQ1 CLK REQ2 MCLK IN CLK OUT1 CLK OUT2 VLDO L L X L L 0 V L H CLK L CLK 1.8 V H L CLK CLK L 1.8 V H H CLK CLK CLK 1.8 V www.onsemi.com 2