NB3N51054 PCIe Clock Generator, Crystal to 100 MHz Quad HCSL / LVDS, 3.3 V The NB3N51054 is a precision, low phase noise clock generator that www.onsemi.com supports PCI Express requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz reference clock signal and generates four differential HCSL/LVDS outputs (See MARKING Figure 7 for LVDS interface) at 100 MHz clock frequency with DIAGRAM 2 maximum skew of 40 ps. Through I C interface, NB3N51054 provides selectable spread spectrum options of 0.35% and 0.5% for NB3N5 applications demanding low Electromagnetic Interface (EMI) as well 1054G 2 as optimum performance with no spread option. The I C interface ALYW TSSOP24 further enables control of each output and they can be enabled/ CASE 948H disabled individually. A = Assembly Location Features L = Wafer Lot Uses 25 MHz Fundamental Crystal or Reference Clock Input Y = Year Four Low Skew HCSL or LVDS Outputs W = Work Week 2 G = PbFree Package I C Support with Read Back Capability Spread of 0.35%, 0.5% and No Spread 2 Individual Output Enable/Disable Control through I C ORDERING INFORMATION PCIe Gen 1, Gen 2, Gen 3, Gen 4 Compliant See detailed ordering and shipping information on page 14 of this data sheet. Typical Phase Jitter 100 MHz (Integrated 12 kHz to 20 MHz): 0.5 ps Typical CycleCycle Jitter 100 MHz (10k cycles): 20 ps Phase Noise 100 MHz: Offset Noise Power 100 Hz 104 dBc/Hz 1 kHz 121 dBc/Hz 10 kHz 131 dBc/Hz 100 kHz 136 dBc/Hz 1 MHz 140 dBc/Hz 10 MHz 155 dBc/Hz Operating Power Supply: 3.3 V 5% Industrial Temperature Range: 40C to 85C Functionally Compatible with ICS841S104I with enhanced performance These are PbFree Devices Application End Products Networking Switch and Router Consumer Set Top Box, LCD TV Computing and Peripherals Servers, Desktop Computers Industrial Equipment Automated Test Equipment PCIe Clock Generation Gen 1, Gen 2, Gen 3 and Gen 4 Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: May, 2018 Rev. 5 NB3N51054/DNB3N51054 BLOCK DIAGRAM V SDATA SCLK DD CLKx OE HCSL CLK3 buffer 2 I C Serial CLK3 Interface SS EN, SS SEL Spread Spectrum CLK2 HCSL XIN/CLKIN buffer CLK2 Clock Buffer/ 25 MHz ref Divider Phase Charge VCO Cystal Oscillator Clock or Detector Pump 25 MHz CLK1 HCSL Crystal XOUT buffer CLK1 Feedback Divider CLK0 HCSL buffer CLK0 GND IREF Figure 1. Block Diagram PIN CONFIGURATION CLK2 CLK3 1 24 CLK2 CLK3 2 23 GND V 3 22 DD V DD 4 21 SDATA CLK1 5 20 SCLK CLK1 6 19 XOUT 1 XIN/CLKIN CLK0 7 18 8 17 V CLK0 DD 16 GND GND 9 V 10 15 NC DD GND 11 14 V DD IREF 13 GND 12 Figure 2. Pin Configuration (Top View) www.onsemi.com 2