NB3N51034 3.3V, Crystal to 100MHz/ 200MHz Quad HCSL/LVDS Clock Generator The NB3N51034 is a high precision, low phase noise clock generator that supports spread spectrum designed for PCI Express applications. This device takes a 25 MHz fundamental mode parallel resonant crystal www.onsemi.com and generates 4 differential HCSL/LVDS outputs at 100MHz or 200 MHz (See Figure 8 for LVDS interface). The NB3N51034 provides MARKING selectable spread options of 0.5%, 1.0%, 1.5%, for applications DIAGRAM demanding low Electromagnetic Interference (EMI) as well as optimum performance with no spread option. NB3N Features 1034 Uses 25 MHz Fundamental Mode Parallel Resonant Crystal ALYW TSSOP20 Power Down Mode DT SUFFIX CASE 948E 4 Low Skew HCSL or LVDS Outputs A = Assembly Location OE TriStates Outputs L = Wafer Lot Spread of 0.5%, 1.0%, 1.5% and No Spread Y = Year PCIe Gen 1, Gen 2, Gen 3, Gen 4 Compliant W = Work Week = PbFree Package Phase Noise (SS OFF) 100 MHz: (Note: Microdot may be in either location) Offset Noise Power 100 Hz 110 dBc/Hz ORDERING INFORMATION 1 kHz 123 dBc/Hz See detailed ordering and shipping information on page 10 of 10 kHz 134 dBc/Hz this data sheet. 100 kHz 137 dBc/Hz 1 MHz 138 dBc/Hz 10 MHz 154 dBc/Hz Operating Supply Voltage Range 3.3 V 5% Computing and Peripherals Industrial Temperature Range 40C to +85C Industrial Equipment Functionally Compatible with IDT55705, PCIe Clock Generation Gen 1, Gen 2, Gen 3 and Gen 4 IDT5V41066, IDT5V41236 with enhanced performance End Products These are PbFree Devices Switch and Router Applications Set Top Box, LCD TV Networking Servers, Desktop Computers Consumer Automated Test Equipment V S0 S1 S2 PD OE DD CLK0 HCSL Spread Spectrum CLK0 Output Circuit CLK1 HCSL CLK1 Output X1/CLK Clock Buffer CLK2 Phase Charge VCO HCSL 25 MHz Clock Crystal Oscillator Detector Pump CLK2 Output or Crystal X2 CLK3 HCSL N CLK3 Output V = VDDODA = VDDXD DD GND IREF GND = GNDODA = GNDXD Figure 1. NB3N51034 Simplified Logic Diagram Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: September, 2017 Rev. 3 NB3N51034/DNB3N51034 VDDXD 1 20 CLK0 S0 2 19 CLK0 S1 3 18 CLK1 S2 4 17 CLK1 X1/CLK 5 16 GNDODA X2 6 15 VDDODA CLK2 7 14 PD OE 8 13 CLK2 CLK3 GNDXD912 IREF 10 11 CLK3 Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Symbol I/O Description 1 VDDXD Power Connect to a +3.3 V source. 2 S0 Input LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDDXD. See output select table 2 for details. 3 S1 Input LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDDXD. See output select Table 2 for details. 4 S2 Input LVTTL/LVCMOS frequency select input 2. Internal pullup resistor to VDDXD. See output select Table 2 for details. 5 X1/CLK Input Crystal interface or single ended reference clock input. 6 X2 Output Crystal interface. Float this pin for reference clock input CLK. 7 PD Input LVTTL/LVCMOS power down input. Assert this pin LOW to enter power down mode. Internal pullup resistor to VDDXD. 8 OE Input Output enable. Tristate output (High=enable outputs, Low=disable outputs). Internal pull up resistor. 9 GNDXD Power Connect to digital circuit ground. 10 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 11 CLK3 HCSL or Inverted clock output. (For LVDS levels see Figure 8) LVDS Output 12 CLK3 HCSL or Noninverted clock output. (For LVDS levels see Figure 8) LVDS Output 13 CLK2 HCSL or Inverted clock output. (For LVDS levels see Figure 8) LVDS Output 14 CLK2 HCSL or Noninverted clock output. (For LVDS levels see Figure 8) LVDS Output 15 VDDODA Power Connect to a +3.3 V analog source. 16 GNDODA Power Output and analog circuit ground. 17 CLK1 HCSL or Inverted clock output. (For LVDS levels see Figure 8) LVDS Output 18 CLK1 HCSL or Noninverted clock output. (For LVDS levels see Figure 8) LVDS Output 19 CLK0 HCSL or Inverted clock output. (For LVDS levels see Figure 8) LVDS Output 20 CLK0 HCSL or Noninverted clock output. (For LVDS levels see Figure 8) LVDS Output www.onsemi.com 2