NB3N4666C 3.3 V Quad LVCMOS Differential Line Receiver Translator Description www.onsemi.com The NB3N4666C is a quadchannel LVDS line receiver/translator offering data rates up to 400 Mbps (200 MHz) and low power consumption. The NB3N4666C receiver incorporates input failsafe MARKING protection circuit that provides a known output voltage under input DIAGRAMS opencircuit and terminated (100 ) conditions. The four independent 16 inputs accept differential signals such as: MLVDS, LVDS, LVPECL NB3N 1 and HCSL and translates them to a singleended, 3.3 V LVCMOS. 4666 TSSOP16 ALYW The NB3N4666C also offers active high and active low DT SUFFIX enable/disable inputs (EN and EN) that allow users to control outputs CASE 948F 1 of all four receivers. These inputs enable or disable the receivers and switch the outputs to an active or high impedance state respectively A = Assembly Location L = Wafer Lot (see Table 2). The high impedance mode feature helps to reduce the Y = Year quiescent power consumption to less than 10 mW typical, when the W = Work Week outputs of one or more NB3N4666C devices are multiplexed together. = PbFree Package (Note: Microdot may be in either location) Features Accepts MLVDS, LVDS, LVPECL and HCSL Differential Input Signal Levels Maximum Data Rate of 400 Mbps NB3N4666C VCC IN4 IN1 Maximum Clock Frequency of 200 MHz IN1 IN4 25 ps Typical ChanneltoChannel Skew R1 R4 3.3 ns Maximum Propagation Delay 3.3 V 10% Power Supply OUT4 OUT1 High Impedance Outputs When Disabled EN EN Low Quiescent Power < 10 mW Typical Supports Open and Terminated Input Failsafe 40C to +85C Ambient Operating Temperature OUT2 OUT3 16Pin TSSOP, 5.0 mm x 4.4 mm x 1.2 mm These are PbFree Devices R2 R3 IN3 IN2 Applications IN2 IN3 Pointtopoint Data Transmission GND Backplane Receivers Figure 1. Functional Block Diagram Clock Distribution Networks Multidrop Buses ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2017 Rev. 1 NB3N4666C/DNB3N4666C Table 1. PIN DESCRIPTION Pin TSSOP Name I/O Description 1 IN1 Input Receiver Channel 1 Inverted Input. 2 IN1 Input Receiver Channel 1 Noninverted Input. 3 OUT1 LVCMOS Output Receiver Channel 1 Output. 4 EN Input Enable Active High Enable. See Table 2 for output enable function. 5 OUT2 LVCMOS Output Receiver Channel 2 Output. 6 IN2 Input Receiver Channel 2 Noninverted Input. 7 IN2 Input Receiver Channel 2 Inverted Input. 8 GND Power Power Supply Ground (Note 1) 9 IN3 Input Receiver Channel 3 Inverted Input. 10 IN3 Input Receiver Channel 3 Noninverted Input. 11 OUT3 LVCMOS Output Receiver Channel 3 Output. 12 EN Inverted Input Active Low Enable. Defaults Low when left open internal pulldown resistor. Enable See Table 2 for output enable function. 13 OUT4 LVCMOS Output Receiver Channel 4 Output. 14 IN4 Input Receiver Channel 4 Noninverted Input. 15 IN4 Input Receiver Channel 4 Inverted Input. 16 V Power 3.3 V 10% Positive Supply Voltage (Note 1) CC 1. All V and GND pins must be externally connected to a power supply for proper operation. Bypass each supply pin with 0.01 F to GND. CC IN1 1 16 VCC IN1 IN4 2 15 OUT1 IN4 3 14 EN OUT4 4 13 OUT2 5 12 EN IN2 OUT3 6 11 IN2 IN3 7 10 IN3 GND 8 9 Figure 2. TSSOP16 Pinout (Top View) www.onsemi.com 2