MC100EP33DTR2 ON Semiconductor

MC10EP33, MC100EP33 3.3V / 5VECL 4 Divider Description The MC10/100EP33 is an integrated 4 divider. The differential clock inputs. The V pin, an internally generated voltage supply, is available to BB MC10EP33, MC100EP33 Table 1. PIN DESCRIPTION PIN FUNCTION RESET 1 8 V CLK*, CLK* ECL Clock Inputs CC R Reset* ECL Asynchronous Reset V Reference Voltage Output BB CLK 2 7 Q Q, Q ECL Data Outputs V Positive Supply 4 CC V Negative Supply EE CLK 3 6 Q EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal con- duit. Electrically connect to the most neg- ative supply (GND) or leave unconnected, V45 V BB EE floating open. * Pins will default LOW when left open. Table 2. TRUTH TABLE Figure 1. 8Lead Pinout (Top View) and Logic Diagram CLK CLK RESET Q Q X X Z L H Z Z L F F Z = LOW to HIGH Transition Z = HIGH to LOW Transition F = Divide by 4 Function CLK t RR RESET Q Figure 2. Timing Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor NA ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg PbFree Pkg SOIC8 Level 1 Level 1 TSSOP8 Level 1 Level 3 DFN8 Level 1 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL94 V0 0.125 in Transistor Count 91 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.