3.3 V/5 VECL D FlipFlop with Set and Reset MC100EP31 Description The MC100EP31 is a D flip-flop with set and reset. The device is www.onsemi.com pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC 8 8 performance available. Both set and reset inputs are asynchronous, 1 level triggered signals. Data enters the master portion of the flip-flop 1 when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. SOIC8 NB TSSOP8 The 100 Series contains temperature compensation. D SUFFIX DT SUFFIX CASE 75107 CASE 948R02 Features 340 ps Typical Propagation Delay Maximum Frequency = > 3 GHz Typical MARKING DIAGRAMS* PECL Mode Operating Range: V = 3.0 V to 5.5 V with V = 0 V CC EE 8 8 NECL Mode Operating Range: KEP31 KP31 V = 0 V with V = 3.0 V to 5.5 V ALYW CC EE ALYW Open Input Default State 1 1 Q Output Will Default LOW with Inputs Open or at V EE SOIC8 NB TSSOP8 These Devices are Pb-Free, Halogen Free and are RoHS Compliant K = MC100 A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100EP31DG SOIC8 NB 98 Units / Tube (Pb-Free) TSSOP8 100 Units / Tube MC100EP31DTG (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: April, 2021 Rev. 12 MC100EP31/DMC100EP31 Table 1. PIN DESCRIPTION SET 1 8 V CC Pin Function CLK* ECL Clock Inputs S Reset* ECL Asynchronous Reset D 2 7 Q D Set* ECL Asynchronous Set D* ECL Data Input Flip Flop Q, Q ECL Data Outputs CLK 3 6 Q V Positive Supply CC R V Negative Supply EE *Pins will default LOW when left open. RESET45 V EE Table 2. TRUTH TABLE D SET RESET CLK Q Figure 1. 8-Lead Pinout (Top View) and L L L Z L Logic Diagram H L L Z H X H L X H X L H X L X H H X UNDEF Z = LOW to HIGH Transition Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8 NB Level 1 TSSOP8 Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 75 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2