MC100EPT25 -3.3 V / -5 VDifferential ECL to +3.3 V LVTTL Translator Description www.onsemi.com The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, 3.3 V to 5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal 8 8 for applications which require the translation of a clock or data signal. 1 1 The V output allows the EPT25 to also be used in a single-ended BB SOIC8NB TSSOP8 input mode. In this mode the V output is tied to the D input for BB DFN8 D SUFFIX DT SUFFIX a inverting buffer or the D input for a non-inverting buffer. If used, the MN SUFFIX CASE CASE V pin should be bypassed to ground with at least a 0.01 F CASE 506AA BB 75107 948R02 capacitor. Features MARKING DIAGRAMS* 1.1 ns Typical Propagation Delay Maximum Frequency > 275 MHz Typical 8 8 Operating Range: KPT25 V = 3.0 V to 3.6 V V = 5.5 V to 3.0 V GND = 0 V KA25 CC EE ALYW ALYW 24 mA TTL Outputs 14 1 Q Output Will Default LOW with Inputs Open or at V 1 EE V Output BB A = Assembly Location Open Input Default State L = Wafer Lot Safety Clamp on Inputs Y = Year W = Work Week These Devices are Pb-Free, Halogen Free and are RoHS Compliant M = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100EPT25DG SOIC8NB 98 Units/Tube (Pb-Free) MC100EPT25DR2G SOIC8NB 2500/Tape & Reel (Pb-Free) MC100EPT25DTG TSSOP8 100 Units/Tube (Pb-Free) MC100EPT25DTR2G TSSOP8 2500/Tape & Reel (Pb-Free) MC100EPT25MNR4G DFN8 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 Rev. 17 MC100EPT25/D 3V M MC100EPT25 Table 1. PIN DESCRIPTION V 1 8 V EE CC PIN FUNCTION Q LVTTL Output D*, D* Differential ECL Input Pair LVTTL D 2 7 Q V Positive Supply CC V Output Reference Voltage BB GND Ground D 3 6 NC V Negative Supply EE LVECL/ECL NC No Connect EP (DFN8 only) Thermal exposed pad V45 GND BB must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Figure 1. 8-Lead Pinout (Top View) and Logic Diagram * Pins will default LOW when left open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating UL94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 111 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2