3.3 V/5 VECL Quad Differential Driver/Receiver MC10EP17, MC100EP17 Description The MC10/100EP17 is a 4-bit differential line receiver based on the www.onsemi.com EP17 device. The > 3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB TSSOP20 and V via a 0.01 F capacitor and limit current sourcing or sinking DT SUFFIX CC CASE 948E to 0.5 mA. When not used, V should be left open. BB The design incorporates two stages of gain, internal to the device, MARKING DIAGRAM* making it an excellent choice for use in high bandwidth amplifier applications. Inputs of unused gates can be left open and will not affect the 20 MCyyyEP17 operation of the rest of the device. All V and V pins must be CC EE AWLYYWWG externally connected to power supply to guarantee proper operation. The 100 Series contains temperature compensation. 1 Features yyy = 10 or 100 A = Assembly Location 220 ps Typical Propagation Delay WL = Wafer Lot Maximum Frequency > 3.0 GHz Typical YY = Year WW = Work Week PECL Mode Operating Range: G = Pb-Free Package V = 3.0 V to 5.5 V with V = 0 V CC EE NECL Mode Operating Range: (Note: Microdot may be in either location) V = 0 V with V = 3.0 V to 5.5 V CC EE *For additional marking information, refer to Application Note AND8002/D. Open Input Default State Safety Clamp on Inputs Q Output Will Default LOW with Inputs Open or at V EE ORDERING INFORMATION V Output BB These Devices are Pb-Free, Halogen Free and are RoHS Compliant Shipping Device Package 75 Units / MC10EP17DTG TSSOP20 WB Tube (Pb-Free) 75 Units / MC100EP17DTG TSSOP20 WB Tube (Pb-Free) Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: April, 2021 Rev. 11 MC10EP17/DMC10EP17, MC100EP17 V Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 V CC EE Table 1. PIN DESCRIPTION 20 19 18 17 16 15 14 13 12 11 PIN FUNCTION D 0:3 *, D 0:3 * ECL Differential Data Inputs Q 0:3 , Q 0:3 ECL Differential Data Outputs V Reference Voltage Output BB V Positive Supply CC V Negative Supply EE * Pins will default LOW when left open. 1 2 3 4 567 8 9 10 V D0 D0 D1 D1 D2 D2 D3 D3 V CC BB Figure 1. 20-Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 2 kV Machine Model > 100 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg TSSOP20 WB Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 259 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2