MC10H125 Quad MECLtoTTL Translator Description The MC10H125 is a quad translator for interfacing data and control signals between the MECL section and saturated logic section of www.onsemi.com digital systems. The 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay, and no increase in power-supply current. Outputs of unused translators will go to low state when their inputs are left open. 16 20 1 1 Features PDIP16 PLLC20 P SUFFIX FN SUFFIX Propagation Delay, 2.5 ns Typical CASE 64808 CASE 77502 Voltage Compensated Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) MARKING DIAGRAMS* MECL 10K Compatible These Devices are Pb-Free, Halogen Free and are RoHS Compliant 120 16 MC10H125P 10H125G AWLYYWWG AWLYYWW 1 PDIP16 PLLC20 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC10H125FNG PLLC20 46 Units / Tube (Pb-Free) MC10H125FNR2G PLLC20 500 Tape & Reel (Pb-Free) MC10H125PG PDIP16 25 Units / Tube (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: August, 2016 Rev. 14 MC10H125/DMC10H125 2 4 3 6 5 7 10 12 11 14 13 15 1 V * BB GND = Pin 16 V ( +5.0 Vdc) = Pin 9 CC V ( 5.2 Vdc) = Pin 8 EE *V to be used to supply bias to the MC10H125 BB only and bypassed (when used) with 0.01 F to 0.1 F capacitor to ground (0 V). V can source < 1.0 mA. BB Figure 1. Logic Diagram GND D D D Exposed Pad (EP) IN IN OUT V 1 16 GND BB 16 15 14 13 A D 2 15 in in V 1 12 C BB OUT A D 3 14 in in A 4 13 D A 2 11 C out out IN IN MC10H125 C B 5 12 out out A 3 10 C IN IN B C 6 11 in in A V OUT 4 9 CC C B 7 10 in in V 8 9 V EE CC 56 7 8 B B B V OUT IN IN EE Pin assignment is for DualinLine Package. For PLCC pin assignment, see the Pin Conversion Tables. Pin assignment for QFN16 Package. Figure 2. Pin Assignment Table 1. DIP CONVERSION TABLES 16Pin DIL to 20Pin PLCC 16 PIN DIL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 PIN PLCC 2 3 4 5 7 8 9 10 12 13 14 15 17 18 19 20 20Pin DIL to 20Pin PLCC 20 PIN DIL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20 PIN PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 www.onsemi.com 2