MC74AC373DWR2G ON Semiconductor

MC74AC373, MC74ACT373 Octal Transparent Latch with 3-State Outputs The MC74AC373/74ACT373 consists of eight latches with 3state outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is www.onsemi.com LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. SOIC20W Features DW SUFFIX CASE 751D Eight Latches in a Single Package 1 3State Outputs for Bus Interfacing Outputs Source/Sink 24 mA TSSOP20 ACT373 Has TTL Compatible Inputs DT SUFFIX CASE 948E These are PbFree Devices 1 V O D D O O D D O LE CC 7 7 6 6 5 5 4 4 ORDERING INFORMATION 20 19 18 17 16 15 14 13 12 11 See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 9 of this data sheet. 1 2 3 4 567 8 9 10 OE O D D O O D D O GND 0 0 1 1 2 2 3 3 Figure 1. Pinout: 20Lead Packages Conductors (Top View) PIN ASSIGNMENT PIN FUNCTION D D Data Inputs 0 7 LE Latch Enable Input OE Output Enable Input O O 3State Latch Outputs 0 7 D D D D D D D D 0 1 2 3 4 5 6 7 LE OE O O O O O O O O 0 1 2 3 4 5 6 7 Figure 2. Logic Symbol Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: February, 2017 Rev. 11 MC74AC373/DMC74AC373, MC74ACT373 FUNCTIONAL DESCRIPTION TRUTH TABLE The MC74AC373/74ACT373 contains eight Dtype Inputs Outputs latches with 3state standard outputs. When the Latch OE LE D O n n Enable (LE) input is HIGH, data on the D inputs enters the n H X X Z latches. In this condition the latches are transparent, i.e., a L H L L latch output will change state each time its D input changes. L H H H When LE is LOW, the latches store the information that was L L X O 0 present on the D inputs a setup time preceding the H = HIGH Voltage Level HIGHtoLOW transition of LE. The 3-state standard L = LOW Voltage Level outputs are controlled by the Output Enable (OE) input. Z = High Impedance X = Immaterial When OE is LOW, the standard outputs are in the 2state O = Previous O before LOW-to-HIGH Transition of Clock 0 0 mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. D D D D D D D D 0 1 2 3 4 5 6 7 D D D D D D D D O O O O O O O O G G G G G G G G LE OE NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram www.onsemi.com 2