MC74AC374, MC74ACT374
Octal D-Type Flip-Flop with
3-State Outputs
The MC74AC374/74ACT374 is a highspeed, lowpower octal
Dtype flipflop featuring separate Dtype inputs for each flipflop
and 3state outputs for busoriented applications. A buffered Clock
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(CP) and Output Enable (OE) are common to all flipflops.
Features
Buffered Positive EdgeTriggered Clock
SOIC20W
3State Outputs for BusOriented Applications
DW SUFFIX
CASE 751D
Outputs Source/Sink 24 mA
1
See MC74AC273 for Reset Version
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
TSSOP20
See MC74AC574 for Broadside Pinout Version
DT SUFFIX
See MC74AC564 for Broadside Pinout Version with Inverted
CASE 948E
Outputs
1
ACT374 Has TTL Compatible Inputs
These are PbFree Devices
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
V O D D O O D D O CP
CC 7 7 6 6 5 5 4 4
20 19 18 17 16 15 14 13 12 11
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1 2 34567 8 9 10
OE O D D O O D D O GND
0 0 1 1 2 2 3 3
Figure 1. Pinout: 20 Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN FUNCTION
D D Data Inputs
0 7
D D D D D D D D
0 1 2 3 4 5 6 7
CP Clock Pulse Input
CP
OE 3State Output Enable Input
OE
O O O O O O O O
0 1 2 3 4 5 6 7
O O 3State Outputs
0 7
Figure 2. Logic Symbol
Semiconductor Components Industries, LLC, 2015
1 Publication Order Number:
March, 2015 Rev. 9 MC74AC374/DMC74AC374, MC74ACT374
FUNCTIONAL DESCRIPTION
TRUTH TABLE
The MC74AC374/74ACT374 consists of eight edge
Inputs Outputs
triggered flipflops with individual Dtype inputs and
D CP OE O
n n
3state true outputs. The buffered clock and buffered Output
H L H
Enable are common to all flipflops. The eight flipflops
L L L
will store the state of their individual D inputs that meet the
X X H Z
setup and hold time requirements on the LOWtoHIGH
H = HIGH Voltage Level
Clock (CP) transition. With the Output Enable (OE) LOW,
L = LOW Voltage Level
the contents of the eight flipflops are available at the
X = Immaterial
outputs. When the OE is HIGH, the outputs go to the high
Z = High Impedance
= LOW-to-HIGH Transition
impedance state. Operation of the OE input does not affect
the state of the flipflops.
D D D D D D D D
0 1 2 3 4 5 6 7
CP
CP D CP D CP D CP D CP D CP D CP D CP D
QQ QQ QQ QQ QQ QQ QQ QQ
OE
O O O O O O O O
0 1 2 3 4 5 6 7
NOTE: That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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2