MC74AC74, MC74ACT74
Dual D-Type Positive
Edge-Triggered Flip-Flop
The MC74AC74/74ACT74 is a dual Dtype flipflop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
www.onsemi.com
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
MARKING
of the positive-going pulse. After the Clock Pulse input threshold
DIAGRAMS
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
14
of the Clock Pulse input.
SOIC14
xxx74G
Asynchronous Inputs:
D SUFFIX
AWLYWW
LOW input to S (Set) sets Q to HIGH level
D
CASE 751A
14
1
LOW input to C (Clear) sets Q to LOW level
D
Clear and Set are independent of clock
1
Simultaneous LOW on C and S makes both Q and Q HIGH
D D
14
Features
xxx
Outputs Source/Sink 24 mA TSSOP14
74
DT SUFFIX ALYW
ACT74 Has TTL Compatible Inputs
1
CASE 948G
These are PbFree Devices
14
1
V
CC C D CP S Q Q
D2 2 2 D2 2 2
14 13 12 11 10 9 8
xxx = AC or ACT
A = Assembly Location
WL or L = Wafer Lot
C S
Y = Year
D1 D2
D Q CP Q
1 1 2 2
WW or W = Work Week
CP Q D Q
1 S 1 2 C 2
D1 D2
G or = PbFree Package
(Note: Microdot may be in either location)
1 2 3 4 567
C D CP S Q Q GND
D1 1 1 D1 1 1
ORDERING INFORMATION
Figure 1. Pinout: 14Lead Packages Conductors
See detailed ordering and shipping information in the package
(Top View)
dimensions section on page 7 of this data sheet.
PIN ASSIGNMENT
PIN FUNCTION
D , D Data Inputs
1 2
CP , CP Clock Pulse Inputs
1 2
C , C Direct Clear Inputs
D1 D2
S , S Direct Set Inputs
D1 D2
Q , Q , Q , Outputs
1 1 2
Q
2
Semiconductor Components Industries, LLC, 2015
1 Publication Order Number:
January, 2015 Rev. 8 MC74AC74/DMC74AC74, MC74ACT74
TRUTH TABLE (Each Half)
Inputs Outputs
Q Q
1 1
S C
D1 D1
S C CP D Q Q
D D
D CP
1 1
L H X X H L
H L X X L H
L L X X H H
H H H H L
H H L L H
Q Q
H H L X Q Q
0 0 2 2
S CD
D2 2
NOTE: H = HIGH Voltage Level
D CP
2 2
L = LOW Voltage Level
X = Immaterial;
= LOW-to-HIGH Clock Transition
Q (Q ) = Previous Q(Q) before LOW-to-HIGH
0 0
Transition of Clock
Figure 2. Logic Symbol
S
D
D Q
CP
Q
C
D
NOTE: This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
Figure 3. Logic Diagram
www.onsemi.com
2