DATA SHEET www.onsemi.com Octal 3-State Noninverting Transparent Latch with SOIC20 TSSOP20 LSTTL Compatible Inputs DW SUFFIX DT SUFFIX CASE 751D CASE 948E HighPerformance SiliconGate CMOS PIN ASSIGNMENT MC74HCT573A OUTPUT 1 ENABLE 20 V CC D0 The MC74HCT573A is identical in pinout to the LS573. This 2 19 Q0 D1 18 Q1 3 device may be used as a level converter for interfacing TTL or NMOS D2 17 Q2 4 outputs to HighSpeed CMOS inputs. D3 16 5 Q3 These latches appear transparent to data (i.e., the outputs change D4 15 Q4 6 asynchronously) when Latch Enable is high. When Latch Enable goes 14 Q5 D5 7 Q6 D6 8 13 low, data meeting the setup and hold times becomes latched. D7 9 12 Q7 The Output Enable input does not affect the state of the latches, but 11 GND 10 LATCH when Output Enable is high, all device outputs are forced to the ENABLE highimpedance state. Thus, data may be latched even when the outputs are not enabled. MARKING DIAGRAMS The HCT573A is identical in function to the HCT373A but has the 20 Data Inputs on the opposite side of the package from the outputs to 20 facilitate PC board layout. HCT HCT573A 573A ALYW Features AWLYYWWG Output Drive Capability: 15 LSTTL Loads 1 1 TTL/NMOSCompatible Input Levels SOIC20 TSSOP20 Outputs Directly Interface to CMOS, NMOS and TTL A = Assembly Location Operating Voltage Range: 4.5 to 5.5 V WL, L = Wafer Lot Low Input Current: 10 A YY, Y = Year WW, W = Work Week In Compliance with the Requirements Defined by JEDEC Standard G or = PbFree Package No. 7 A (Note: Microdot may be in either location) Chip Complexity: 234 FETs or 58.5 Equivalent Gates Improved Propagation Delays ORDERING INFORMATION 50% Lower Quiescent Power Device Package Shipping These Devices are PbFree and are RoHS Compliant MC74HCT573ADWR2G SOIC20 1000 / (PbFree) Tape & Reel LOGIC DIAGRAM MC74HCT573ADTR2G TSSOP20 2500 / (PbFree) Tape & Reel 219 D0 Q0 3 18 MC74HCT573ADWG SOIC20 38 Units / D1 Q1 (PbFree) Rail 4 17 D2 Q2 NLV74HCT573ADTRG TSSOP20 2500 / 5 16 NONINVERTING DATA D3 Q3 (PbFree) Tape & Reel 6 15 OUTPUTS INPUTS D4 Q4 NLV74HCT573ADWG SOIC20 38 Units / 7 14 D5 Q5 (PbFree) Rail 8 13 D6 Q6 NLV74HCT573ADWRG SOIC20 1000 / 9 12 (PbFree) Tape & Reel D7 Q7 For information on tape and reel specifications, 11 LATCH ENABLE including part orientation and tape sizes, please PIN 20 = V CC refer to our Tape and Reel Packaging Specification 1 OUTPUT ENABLE PIN 10 = GND Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: January, 2022 Rev. 14 MC74HCT573A/DMC74HCT573A FUNCTION TABLE Inputs Output Output Latch Enable Enable D Q LH H H LH L L L L X No Change HX X Z X = Dont Care Z = High Impedance Design Criteria Value Units Internal Gate Count* 58.5 ea Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 W Speed Power Product 0.0075 pJ *Equivalent to a twoinput NAND gate. MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage V DC Supply Voltage (Referenced to GND) 0.5 to + 7.0 V CC due to high static voltages or electric V DC Input Voltage (Referenced to GND) 0.5 to V + 0.5 V fields. However, precautions must in CC be taken to avoid applications of any V DC Output Voltage (Referenced to GND) 0.5 to V + 0.5 V out CC voltage higher than maximum rated I DC Input Current, per Pin 20 mA voltages to this highimpedance cir- in cuit. For proper operation, V and in I DC Output Current, per Pin 25 mA out V should be constrained to the out range GND (V or V ) V . I DC Supply Current, V and GND Pins 50 mA CC CC in out CC Unused inputs must always be P Power Dissipation in Still Air SOIC Package 500 mW D tied to an appropriate logic voltage TSSOP Package 450 level (e.g., either GND or V ). CC Unused outputs must be left open. T Storage Temperature 65 to +150 C stg T Lead Temperature, 1 mm from Case for 10 Seconds C L (TSSOP or SOIC Package) 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating: SOIC Package: 7 mW/ C from 65 to 125 C TSSOP Package: 6.1 mW/C from 65 to 125 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V DC Supply Voltage (Referenced to GND) 4.5 5.5 V CC V , V DC Input Voltage, Output Voltage (Referenced to GND) 0 V V in out CC T Operating Temperature, All Package Types 55 +125 C A t , t Input Rise and Fall Time (Figure 1) 0 500 ns r f Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2