Quad 2-Input NAND Gate MC74VHCT00A The MC74VHCT00A is an advanced high speed CMOS 2input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation while maintaining CMOS low power dissipation. www.onsemi.com The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. MARKING DIAGRAMS The device input is compatible with TTLtype input thresholds and the output has a full 5 V CMOS level output swing. The input protection 14 circuitry on this device allows overvoltage tolerance on the input, 14 VHCT00AG allowing the device to be used as a logiclevel translator from 3.0 V 1 AWLYWW CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V SOIC14 1 CMOS Logic while operating at the highvoltage power supply. D SUFFIX CASE 751A The MC74VHCT00A input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHCT00A to be used to interface 5 V circuits to 3 V 14 14 circuits. The output structures also provide protection when V = 0 V. CC VHCT These input and output structures help prevent device destruction caused 1 00A by supply voltage input/output voltage mismatch, battery backup, hot ALYW TSSOP14 insertion, etc. DT SUFFIX CASE 948G 1 High Speed: t = 5.0 ns (Typ) at V = 5 V PD CC Low Power Dissipation: I = 2 A (Max) at T = 25C CC A A = Assembly Location WL, L = Wafer Lot TTLCompatible Inputs: V = 0.8 V V = 2.0 V IL IH YY, Y = Year Power Down Protection Provided on Inputs and Outputs WW, W = Work Week G or = PbFree Package Balanced Propagation Delays (Note: Microdot may be in either location) Designed for 3.0 V to 5.5 V Operating Range Low Noise: V = 0.8 V (Max) OLP Pin and Function Compatible with Other Standard Logic Families ORDERING INFORMATION See detailed ordering and shipping information in the Chip Complexity: 48 FETs or 12 Equivalent Gates dimensions section on page 6 of this data sheet. NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable These Devices are PbFree and are RoHS Compliant Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: February, 2020 Rev. 7 MC74VHCT00A/DMC74VHCT00A 1 A1 3 Y1 2 B1 V B4 A4 Y4 B3 A3 Y3 CC 4 14 13 12 11 10 9 8 A2 6 Y2 5 B2 Y = AB 9 A3 8 Y3 10 B3 12 A4 1 2 3456 7 11 Y4 13 B4 A1 B1 Y1 A2 B2 Y2 GND Figure 1. Pin Assignment Figure 2. Logic Diagram (Top View) FUNCTION TABLE PIN ASSIGNMENT Inputs Output 1 IN A1 AB Y 2 IN B1 L L H 3 OUT Y1 L H H H L H 4 IN A2 H H L 5 IN B2 6 OUT Y2 7 GND A1 1 8 OUT Y3 & 3 Y1 B1 2 9 IN A3 A2 4 10 IN B3 6 Y2 B2 5 11 OUT Y4 A3 9 Y3 8 12 IN A4 B3 10 13 IN B4 A4 12 Y4 11 14 V B4 13 CC Figure 3. IEC LOGIC DIAGRAM www.onsemi.com 2