MM74HCT273 Octal D-Type Flip-Flop with Clear February 1984 Revised May 2005 MM74HCT273 Octal D-Type Flip-Flop with Clear General Description Features The MM74HCT273 utilizes advanced silicon-gate CMOS Typical propagation delay: 20 ns technology. It has an input threshold and output drive simi- Low quiescent current: 80 PA maximum (74HCT series) lar to LS-TTL with the low standby power of CMOS. Fanout of 10 LS-TTL loads These positive edge-triggered flip-flops have a common clock and clear-independent Q outputs. Data on a D input, having the specified set-up and hold time, is transferred to the corresponding Q output on the positive-going transition of the clock pulse. The asynchronous clear forces all out- puts LOW when it is LOW. All inputs to this device are protected from damage due to electrostatic discharge by diodes to V and ground. CC MM74HCT devices are intended to interface TTL and NMOS components to CMOS components. These parts can be used as plug-in replacements to reduce system power consumption in existing designs. Ordering Code: Package Order Number Package Description Number MM74HCT273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HCT273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View 2005 Fairchild Semiconductor Corporation DS005760 www.fairchildsemi.comTruth Table (Each Flip-Flop) Inputs Outputs Clear Clock D Q LX X L H n HH H n LL HL X Q0 H HIGH Level (steady-state) L LOW Level (steady-state) X Dont Care n Transition from LOW-to-HIGH level Q0 The level of Q before the indicated steady-state input conditions were established. Logic Diagram www.fairchildsemi.com 2 MM74HCT273