NB3L204K 2.5V, 3.3V Differential 1:4 HCSL Fanout Buffer Description The NB3L204K is a differential 1:4 Clock fanout buffer with Highspeed Current Steering Logic (HCSL) outputs. Inputs can www.onsemi.com directly accept differential LVPECL, LVDS, and HCSL signals. Singleended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 MARKING and 6. The input signal will be translated to HCSL and provides four DIAGRAM identical copies operating up to 350 MHz. 1 The NB3L204K is optimized for ultralow phase noise, propagation NB3L QFN24 204K delay variation and low outputtooutput skew, and is DB400H 4x4 ALYW CASE 485DJ compliant. As such, system designers can take advantage of the NB3L204Ks performance to distribute low skew clocks across the backplane or the motherboard making it ideal for Clock and Data NB3L204K = Specific Device Code distribution applications such as PCI Express, FBDIMM, Networking, A = Assembly Location Mobile Computing, Gigabit Ethernet, etc. L = Wafer Lot Output drive current is set by connecting a 475 resistor from Y = Year W = Work Week IREF (Pin 14) to GND per Figure 11. Outputs can also interface to = PbFree Package LVDS receivers when terminated per Figure 12. (Note: Microdot may be in either location) Features Maximum Input Clock Frequency > 350 MHz ORDERING INFORMATION 2.5 V 5% / 3.3 V 10% Supply Voltage Operation See detailed ordering and shipping information page 13 of this 4 HCSL Outputs data sheet. DB400H Compliant PCIe Gen 3, Gen 4 Compliant Individual OE Control Pin for Each Output 100 ps Max OutputtoOutput Skew Performance 1 ns Typical Propagation Delay 500 ps Typical Rise and Fall Times 80 fs Maximum Additive RMS Phase Jitter 40C to +85C Ambient Operating Temperature QFN 24pin Package, 4 mm x 4 mm These Devices are PbFree and are RoHS Compliant Typical Applications PCI Express FBDIMM Mobile Computing Networking Gigabit Ethernet Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: October, 2017 Rev. 1 NB3L204K/DNB3L204K VDD VDD O OE0 DIF 0 DIF 0 OE1 DIF 1 DIF 1 CLK IN CLK IN OE2 DIF 2 DIF 2 OE3 DIF 3 DIF 3 I REF R REF Figure 1. Simplified Block Diagram Figure 2. 24Pin QFN Pinout (Top View) www.onsemi.com 2