NB3L208K 2.5V, 3.3V Differential 1:8 HCSL Fanout Buffer Description The NB3L208K is a differential 1:8 Clock fanout buffer with Highspeed Current Steering Logic (HCSL) outputs. Inputs can www.onsemi.com directly accept differential LVPECL, LVDS, and HCSL signals. Singleended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 MARKING and 6. The input signal will be translated to HCSL and provides eight DIAGRAM identical copies operating up to 350 MHz. 1 The NB3L208K is optimized for ultralow phase noise, propagation NB3L 1 32 delay variation and low outputtooutput skew, and is DB800H 208K compliant. As such, system designers can take advantage of the AWLYYWWG QFN32 NB3L208Ks performance to distribute low skew clocks across the G SUFFIX CASE 488AM backplane or the motherboard making it ideal for Clock and Data distribution applications such as PCI Express, FBDIMM, Networking, A = Assembly Location Mobile Computing, Gigabit Ethernet, etc. WL = Wafer Lot YY = Year Output drive current is set by connecting a 475 resistor from WW = Work Week IREF (Pin 27) to GND per Figure 11. Outputs can also interface to G = PbFree Package LVDS receivers when terminated per Figure 12. Features ORDERING INFORMATION Maximum Input Clock Frequency > 350 MHz See detailed ordering and shipping information page 12 of this data sheet. 2.5 V 5% / 3.3 V 10% Supply Voltage Operation 8 HCSL Outputs DB800H Compliant PCIe Gen 3, Gen 4 Compliant Individual OE Control Pin for Each Bank of 2 Outputs 100 ps Max OutputtoOutput Skew Performance 1 ns Typical Propagation Delay 500 ps Typical Rise and Fall Times 80 fs Maximum Additive RMS Phase Jitter 40C to +85C Ambient Operating Temperature QFN 32pin Package, 5 mm x 5 mm These Devices are PbFree and are RoHS Compliant Typical Applications PCI Express FBDIMM Mobile Computing Networking Gigabit Ethernet Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: October, 2017 Rev. 3 NB3L208K/DNB3L208K VDD VDD O OE 1:0 DIF 0 DIF 0 DIF 1 DIF 1 OE 3:2 DIF 2 DIF 2 DIF 3 DIF 3 CLK IN CLK IN OE 5:4 DIF 4 DIF 4 DIF 5 DIF 5 OE 7:6 DIF 6 DIF 6 DIF 7 DIF 7 I REF R REF Figure 1. Simplified Block Diagram Exposed Pad (EP) DIF 0 DIF 4 1 24 DIF 0 DIF 4 23 2 DIF 1 DIF 5 3 22 DIF 1 DIF 5 4 21 NB3L208K DIF 2 20 DIF 6 5 DIF 2 DIF 6 6 19 DIF 7 DIF 3 7 18 DIF 3 DIF 7 8 17 Figure 2. 32Pin QFN Pinout (Top View) www.onsemi.com 2 32 VDD 0 9 VDD 0 31 GND 0 10 OE 7:6 11 30 CLK IN OE 5:4 29 OE 3:2 CLK IN 12 OE 1:0 GND 13 28 14 27 VDD I REF 26 GND 0 15 GND 0 VDD 0 16 25 VDD 0