NB3N200S 3.3 V Differential Multipoint Low Voltage M-LVDS Driver Receiver Description www.onsemi.com The NB3N200 is a pure 3.3 V supply differential Multipoint Low Voltage (MLVDS) line Driver and Receiver. NB3N200S is MARKING TIA/EIA899 compliant. NB3N200S offers the Type 1 receiver 8 DIAGRAM threshold at 0.0 V. 1 8 These devices has a Type1 receiver that detect the bus state with as NB20x SOIC8 little as 50 mV of differential input voltage over a commonmode AYWW D SUFFIX voltage range of 1 V to 3.4 V. The Type1 receivers have near zero CASE 751 1 thresholds (50 mV) and exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. NB20x = Specific Device Code NB3N200S supports Simplex or Half Duplex bus configurations. x = 0, 2, 4, 5 A = Assembly Location Y = Year WW = Work Week G or = PbFree Package ORDERING INFORMATION Features See detailed ordering and shipping information in the package LowVoltage Differential 30 to 55 Line Drivers and Receivers dimensions section on page 17 of this data sheet. for Signaling Rates Up to 200 Mbps Type1 Receivers Incorporate 25 mV of Hysteresis Meets or Exceeds the MLVDS Standard TIA/EIA899 PbFree SOIC 8 Package for Multipoint Data Interchange These are PbFree Devices Controlled Driver Output Voltage Transition Times for Applications Improved Signal Quality LowPower HighSpeed ShortReach Alternative to 1 V to 3.4 V CommonMode Voltage Range Allows TIA/EIA485 Data Transfer With up to 2 V of Ground Noise Backplane or Cabled Multipoint Data and Clock Bus Pins High Impedance When Disabled or V CC Transmission 1.5 V Cellular Base Stations MLVDS Bus Power Up/Down Glitch Free CentralOffice Switches Operating range: V = 3.3 10% V( 3.0 to 3.6 V) CC Network Switches and Routers Operation from 40C to 85C. Figure 1. Logic Diagrams Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: June, 2015 Rev. 1 NB3N200S/DNB3N200S R V 1 8 CC RE B 2 7 DE 3 A 6 4 D GND 5 SOIC8 NB3N200S Figure 2. Pinout Diagrams (Top View) Table 1. PIN DESCRIPTION SOIC8 Number Name I/O Type Open Default Description 1 R LVCMOS Output Receiver Output Pin 2 RE LVCMOS Input High Receiver Enable Input Pin (LOW = Active, HIGH = High Z Output) 3 DE LVCMOS Input Low Driver Enable Input Pin (LOW = High Z Output, HIGH = Active) 4 D LVCMOS Input Driver Output Pin 5 GND Ground Supply pin. Pin must be externally connected to power supply to guarantee proper operation. 6 A MLVDS Input / Transceiver Invert Input / Output Pin Output 7 B MLVDS Input / Transceiver True Input / Output Pin Output 8 VCC Power Supply pin. Pin must be externally connected to power supply to guarantee proper operation. Table 2. DEVICE FUNCTION TABLE Inputs Output V = V V RE R ID A B V 50 mV L H ID 50 mV < V < 50 mV L ID TYPE 1 Receiver (NB3N200) V 50 mV L L ID X H Z X Open Z Open L Input Enable Output D DE A / Y B / Z L H L H H H H L DRIVER Open H L H X Open Z Z X L Z Z H = High, L = Low, Z = High Impedance, X = Dont Care, = Indeterminate www.onsemi.com 2