NB3N2302DG ON Semiconductor

NB3N2302 3.3V / 5V 5MHz to 133MHz Frequency Multiplier and Zero Delay Buffer Description NB3N2302 FBIN 1 8 OUT2 REF IN 2 7 V DD GND 3 6 OUT1 FS0 45 FS1 Figure 2. NB3N2302 Package Pinout (Top View) 8pin SOIC (150 mil) Table 1. CLOCK MULTIPLIER SELECT TABLE REF IN Min REF IN Max (MHz) (MHz) FBIN FS0 FS1 OUT1 OUT2 OUT1 0 0 2 x REF REF 5 66.5 OUT1 1 0 4 x REF 2 x REF 5 33.25 OUT1 0 1 REF REF / 2 10 133 OUT1 1 1 8 x REF 4 x REF 5 16.625 OUT2 0 0 4 x REF 2 x REF 5 33.25 OUT2 1 0 8 x REF 4 x REF 5 16.625 OUT2 0 1 2 x REF REF 5 66.5 OUT2 1 1 16 x REF 8 x REF 5 8.3125 Table 2. PIN DESCRIPTION Pin Name Pin Type Description 1 FBIN LVCMOS/LVTTL Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure Input proper functionality. If the trace between FBIN and the output pin being used for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations are synchronized to the REF signal input (REF IN). 2 REF IN LVCMOS/LVTTL Reference Input: The output signals are synchronized to this signal. Input 3 GND Power Negative supply voltage Connect to ground, 0 V 4 FS0 LVCMOS/LVTTL Function Select Input: Tie to V (HIGH, 1) or GND (LOW, 0) as desired per Table 1. DD Input 5 FS1 LVCMOS/LVTTL Function Select Input: Tie to V (HIGH, 1) or GND (LOW, 0) as desired per Table 1. DD Input 6 OUT1 LVCMOS/LVTTL Output 1: The frequency of the signal provided by this pin is determined by the feedback Output signal connected to FBIN, and the FS0:1 inputs (see Table 1). 7 VDD Power Positive supply voltage This pin should be bypassed with a 0.1 F decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance. 8 OUT2 LVCMOS/LVTTL Output 2: The frequency of the signal provided by this pin is one half of the frequency of Output OUT1. See Table 1.