NB3W1900LMNG ON Semiconductor

NB3W1900L 3.3 V 100/133 MHz Differential 1:19 HCSL-Compatible PushPull Clock ZDB/Fanout Buffer for www.onsemi.com PCIe Description The NB3W1900L differential clock buffers are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide 1 72 point-to-point clocks to multiple agents. The device is capable of QFN72 distributing the reference clocks for Intel QuickPath Interconnect MN SUFFIX (Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4.The NB3W1900L CASE 485DK internal PLL is optimized to support 100 MHz and 133MHz frequency operation. The NB3W1900L is developed with the MARKING DIAGRAM low-power NMOS Push-Pull buffer type. Features 1 19 Low Power Differential Clock Output Pairs 0.7V NB3W 1900L Output-to-Output Skew Performance: < 85 ps AWLYYWWG Cycle-to-Cycle Jitter (PLL Mode): < 50ps 100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2/Gen3/Gen4 and Intel QPI & UPI Phase Jitter A = Assembly Location Input-to-Output Delay Variation: < 50 ps WL = Wafer Lot Fixed-Feedback for Lowest Input-to-Output Delay Variation YY = Year WW = Work Week Spread Spectrum Compatible Tracks Input Clock Spreading for Low G = Pb-Free Package EMI Individual OE Control via SMBus Low-Power NMOS Push-Pull HCSLCompatible Outputs ORDERING INFORMATION See detailed ordering and shipping information on page 19 of PLL Configurable for PLL Mode or Bypass Mode this data sheet. (Fanout Operation) SMBus Address Configurable to Allow Multiple Buffers in a Single Control Network Programmable PLL Bandwidth Two Tri-level Addresses Selection (Nine SMBus Addresses) QFN 72-pin Package, 10 mm 10 mm These are Pb-Free Devices Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: January, 2018 Rev. 3 NB3W1900L/DNB3W1900L FBOUT NC FBOUT NC DIF 18:0 SSC Compatible MUX PLL DIF 18:0 CLK IN CLK IN 100M 133M HBW BYP LBW SA 0 Control SA 1 Logic PWRGD/PWRDN SDA SCL Figure 1. Simplified Block Diagram 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDDA DIF12 1 54 GNDA DIF12 2 53 100M 133M VDDIO 3 52 HBW BYP LBW GND 4 51 DIF11 PWRGD/PWRDN 5 50 GND DIF11 6 49 VDDR DIF10 7 48 DIF10 CLK IN 8 47 NB3W1900L CLK IN GND 9 46 VDD SA 0 10 45 DIF9 SDA 11 44 SCL DIF9 12 43 DIF8 SA 1 13 42 FBOUT NC 14 41 DIF8 VDDIO FBOUT NC 15 40 GND GND 16 39 DIF0 17 38 DIF7 18 37 DIF7 DIF0 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Figure 2. Pin Configuration (Top View) www.onsemi.com 2 DIF1 DIF18 DIF1 DIF18 VDDIO GND GND VDDIO DIF2 DIF17 DIF2 DIF17 DIF16 DIF3 DIF3 DIF16 GND VDD VDD GND DIF4 DIF15 DIF4 DIF15 DIF5 DIF14 DIF5 DIF14 VDDIO GND GND VDDIO DIF6 DIF13 DIF6 DIF13