NB7L1008 2.5V / 3.3V 1:8 LVPECL Fanout Buffer MultiLevel Inputs w/ Internal Termination NB7L1008 Exposed Pad (EP) 32 31 30 29 28 27 26 25 VCC 1 24 GND 2 23 GND VCC Q3 22 3 IN VT 4 21 Q3 NB7L1008 5 20 VREFAC Q4 IN 6 19 Q4 7 GND 18 VCC VCC 8 17 GND 9 10 11 12 13 14 15 16 Figure 1. 32Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 3, 6 IN, IN LVPECL, CML, Noninverted / Inverted Differential Clock/Data Input. Note 1 LVDS Input 4 VT Internal 50 Termination Pin for IN and IN 2, 7 17,24 GND Negative Supply Voltage, Note 2 1, 8, 9, 16, 18, V Positive Supply Voltage, Note 2 CC 23, 25, 32 31, 30, 29, 28, Q0, Q0, Q1, LVPECL Noninverted / Inverted Differential Output. 27, 26, 22, 21, Q1, Q2, Q2, 20, 19, 15, 14, Q3, Q3, Q4, 13, 12, 11, 10 Q4, Q5, Q5, Q6, Q6, Q7, Q7 5 VREFAC Output Voltage Reference for CapacitorCoupled Inputs, only EP The Exposed Pad (EP) on the QFN32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be at- tached to a heatsinking conduit. The pad is electrically connected to GND and is recommended to be electrically connected to GND on the PC board. 1. In the differential configuration when the input termination pin (V ) is connected to a common termination voltage or left open, and if no signal T is applied on IN/IN, then the device will be susceptible to selfoscillation. 2. All V and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation. CC