NB7V52MMNHTBG ON Semiconductor

NB7V52M D Flip Flop, 1.8 V / 2.5 V Differential, with Reset and CML Outputs MultiLevel Inputs w/ Internal Termination NB7V52M Exposed Pad (EP) VTR R R VTR Table 1. INPUT/OUTPUT SELECT TRUTH TABLE 16 15 14 13 R D CLK Q H x x L VTD 1 12 VCC L L Z L D 2 11 Q L H Z H NB7V52M Z = LOW to HIGH Transition D Q 3 10 x = Dont care VTD VEE 4 9 56 7 8 VTCLK CLK CLK VTCLK Figure 2. Pin Configuration (Top View) Table 1. Pin Description Pin Name I/O Description 1 VTD Internal 50 Termination Pin for D 2 D LVPECL, CML, Noninverted Differential Data Input. (Note 1) LVDS Input 3 D LVPECL, CML, Inverted Differential Data Input. (Note 1) LVDS Input 4 VTD Internal 50 Termination Pin for D 5 VTCLK Internal 50 Termination Pin for CLK 6 CLK LVPECL, CML, Noninverted Differential Clock Input. (Note 1) LVDS Input 7 CLK LVPECL, CML, Inverted Differential Clock Input. (Note 1) LVDS Input 8 VTCLK Internal 50 Termination Pin for CLK 9 VEE Negative Supply Voltage. (Note 2) 10 Q CML Output Inverted Differential Output 11 Q CML Output Noninverted Differential Output 12 VCC Positive Supply Voltage. (Note 2) 13 VTR Internal 50 Termination Pin for R 14 R LVPECL, CML, Noninverted Asynchronous Differential Reset Input. (Note 1) LVDS Input 15 R LVPECL, CML, Inverted Asynchronous Differential Reset Input. (Note 1) LVDS Input 16 VTR Internal 50 Termination Pin for R EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is electrically connected to the die, and must be electrically and thermally con- nected to VEE on the PC board. 1. In the differential configuration when the input termination pins (VTx, VTx) are connected to a common termination voltage or left open, and if no signal is applied on CLK/CLK input, then the device will be susceptible to selfoscillation. 2. All VCC and VEE pins must be externally connected to a power supply for proper operation.