NC7SZ10L6X ON Semiconductor

TinyLogic UHS 3-Input NAND Gate NC7SZ10 Description The NC7SZ10 is a single 3 Input NAND Gate from ONSemiconductors Ultra High Speed Series of TinyLogic. The www.onsemi.com device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive while maintaining low static power MARKING dissipation over a broad V operating range. The device is specified CC DIAGRAMS to operate over the 1.65 V to 5.5 V V operating range. The inputs CC and output are high impedance when V is 0 V. Inputs tolerate CC SIP6 1.45x1.0 E6KK voltages up to 5.5 V independent of V operating voltage. CC CASE 127EB XYZ Features Pin 1 Space Saving SC88 6Lead Package Ultra Small MicroPak Leadless Package 6 Ultra High Speed: t = 2.4 ns Typ into 50 pF at 5 V V SC88 PD CC CASE 419B02 Z10M High Output Drive: 24 mA at 3 V V CC Broad V Operating Range: 1.65 V 5.5 V CC 1 Power Down High Impedance Inputs / Output Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation E6, Z10 = Specific Device Code Patented Noise / EMI Reduction Circuitry Implemented KK = 2Digit Lot Run Traceability Code XY = 2Digit Date Code Format These Devices are PbFree, Halogen Free/BFR Free and are RoHS Z = Assembly Plant Code Compliant M = Data Code* = PbFree Package IEEC / IEC (Note: Microdot may be in either location) A & Y *Date Code orientation and/or position may B vary depending upon manufacturing location. C Figure 1. Logic Symbol ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. Semiconductor Components Industries, LLC, 2004 1 Publication Order Number: January, 2021 Rev. 2 NC7SZ10/DNC7SZ10 Connection Diagrams A 1 6 C AC1 6 GND 2 5 V GND 2 5 V CC CC BY3 4 B 3 4 Y Figure 2. SC88 (Top View) Figure 4. MicroPak (Top Through View) (Top View) AAA Pin One AAA represents Product Code Top Mark see ordering code. NOTE: Orientation of Top Mark determines Pin One location. Read the Top Product Code Mark left to right, Pin One is the lower left pin (see diagram). Figure 3. Pin 1 Orientation PIN DESCRIPTIONS FUNCTION TABLE (Y = ABC) Pin Name Description Inputs Output A, B, C Inputs A B C Y Y Output X X L H X L X H L X X H H H H L H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level www.onsemi.com 2