TinyLogic UHS Dual 2-Input NAND Gate NC7WZ00 Description The NC7WZ00 is a dual 2 Input NAND Gate from ONSemicoductors Ultra High Speed Series of TinyLogic. The www.onsemi.com device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive while maintaining low static power MARKING dissipation over a broad V operating range. The device is specified CC DIAGRAMS to operate over the 1.65 V to 5.5 V V operating range. The inputs CC and output are high impedance when V is 0 V. Inputs tolerate CC UQFN8 N6KK voltages up to 5.5 V independent of V operating voltage. CC 1.6X1.6, 0.5P XYZ CASE 523AY Features Space Saving US8 Surface Mount Package MicroPak Leadless Package Ultra High Speed: t 2.4 ns Typ. into 50 pF at 5 V V PD CC WZ00 High Output Drive: 24 mA at 3 V V US8 CC ALYW CASE 846AN Broad V Operating Range: 1.65 V 5.5 V CC Matches the Performance of LCX when Operated at 3.3 V V CC Power Down High Impedance Inputs / Output Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation Proprietary Noise / EMI Reduction Circuitry Implemented N6, WZ00 = Specific Device Code KK = 2Digit Lot Run Traceability Code These Devices are PbFree, Halogen Free/BFR Free and are RoHS XY = 2Digit Date Code Format Compliant Z = Assembly Plant Code A = Assembly Site L = Wafer Lot Number YW = Assembly Start Week IEEE/IEC A & 1 ORDERING INFORMATION Y 1 B 1 See detailed ordering, marking and shipping information in the A & package dimensions section on page 6 of this data sheet. 2 Y 2 B 2 Figure 1. Logic Symbol Semiconductor Components Industries, LLC, 2000 1 Publication Order Number: October, 2020 Rev. 3 NC7WZ00/DNC7WZ00 Pin Configurations A 1 8 V 1 CC A B Y 1 1 2 7 6 5 B 2 7 Y 1 1 Y 3 6 B 2 2 V 8 4 GND CC GND45 A 2 1 2 3 Y B A 1 2 2 Figure 2. Connection Diagram (Top View) Figure 4. Pad Assignments for MicroPak (Top Thru View) (Top View) AAA Pin One AAA represents Product Code Top Mark see ordering code NOTE: Orientation of Top Mark determines Pin One location. Read the top product code mark left to right, Pin One is the lower left pin (see diagram). Figure 3. Pin One Orientation Diagram PIN DESCRIPTION FUNCTION TABLE (Y = AB) Pin Names Description Inputs Output A , B Inputs A B Y n n Y Output L L H n L H H H L H H H L H = HIGH Logic Level L = LOW Logic Level www.onsemi.com 2