NC7WZ132L8X ON Semiconductor

TinyLogic UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs NC7WZ132 Description www.onsemi.com The NC7WZ132 is a dual 2 Input NAND Gate with Schmitttrigger inputs from ON Semiconductors Ultra High Speed MARKING Series of TinyLogic. The device is fabricated with advanced CMOS DIAGRAMS technology to achieve ultra high speed with high output drive while maintaining low static power dissipation over a broad V operating CC UQFN8 range. The device is specified to operate over the 1.65 V to 5.5 V V T5KK CC 1.6X1.6, 0.5P XYZ operating range. The inputs and output are high impedance when V CC CASE 523AY is 0 V. Inputs tolerate voltages up to 5.5 V independent of V CC operating voltage. Schmitt trigger inputs achieve typically 1 V hysteresis between the positive going and negative going input threshold voltage at 5 V V . CC XYKK WZD2 Features US8 Z CASE 846AN ON Space Saving US8 Surface Mount Package MicroPak Leadless Package Ultra High Speed: t = 3.1 ns Typ. into 50 pF at 5 V V PD CC High Output Drive: 24 mA at 3 V V CC T5, WZD2 = Specific Device Code Broad V Operating Range: 1.65 V to 5.5 V CC KK = 2Digit Lot Run Traceability Code XY = 2Digit Date Code Format Matches the Performance of LCX when Operated at 3.3 V V CC Z = Assembly Plant Code Power Down High Impedance Inputs / Output Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation ORDERING INFORMATION Proprietary Noise / EMI Reduction Circuitry Implemented See detailed ordering, marking and shipping information in the Schmitt Trigger Inputs are Tolerant of Slow Changing Input Signals package dimensions section on page 6 of this data sheet. These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant IEEE/IEC A & 1 Y 1 B 1 A 2 Y 2 B 2 Figure 1. Logic Symbol Semiconductor Components Industries, LLC, 2000 1 Publication Order Number: February, 2021 Rev. 3 NC7WZ132/DNC7WZ132 Connection Diagram A 1 8 V A B Y 1 CC 1 1 2 7 6 5 B 2 7 Y 1 1 V 8 4 GND CC Y 3 6 B 2 2 GND45 A 2 1 2 3 Y B A 1 2 2 Figure 2. Connection Diagram (Top View) Figure 4. Pad Assignments for MicroPak (Top Thru View) (Top View) AAA Pin One AAA represents Product Code Top Mark see ordering code NOTE: Orientation of Top Mark determines Pin One location. Read the top product code mark left to right, Pin One is the lower left pin (see diagram). Figure 3. Pin One Orientation Diagram PIN DESCRIPTION FUNCTION TABLE (Y = AB) Pin Names Description Inputs Output A , B Inputs A B Y n n Y Output L L H n L H H H L H H H L H = HIGH Logic Level L = LOW Logic Level www.onsemi.com 2