NCP1595MNR2G ON Semiconductor

NCP1595, NCP1595A, NCP1595C Buck Regulator- Synchronous 1 MHz, 1.5 A NCP1595, NCP1595A, NCP1595C BLOCK DIAGRAM NCP1595/A/C VCCP VCC + CA Power Reset UVLO NC/EN THD Hiccup OSC + PMOS SoftStart M1 + PWM Control LX Logic Vref gm + + FB GND Figure 1. Block Diagram PIN DESCRIPTIONS Pin No Symbol Description 1 FB Feedback input pin of the Error Amplifier. Connect a resistor divider from the converters output volt- age to this pin to set the converters output voltage. 2 GND Ground pin. Connect to thermal pad. 3 LX The drains of the internal MOSFETs. The output inductor should be connected to this pin. 4 V Power input for the power stage CCP 5 V Input supply pin for internal bias circuitry. A 0.1 F ceramic bypass capacitor is preferred to connect CC to this pin. 6 NC No connection for NCP1595 or NCP1595C EN Logic input to enable the part. Logic high to turn on the part and logic low to shut off the part. An internal pullup forces the part into an enable state when no external bias is present on the pin. For NCP1595A only EP PAD Exposed pad of the package provides both electrical contact to the ground and good thermal contact to the PCB. This pad must be soldered to the PCB for proper operation.